JPH03104141A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03104141A JPH03104141A JP24116289A JP24116289A JPH03104141A JP H03104141 A JPH03104141 A JP H03104141A JP 24116289 A JP24116289 A JP 24116289A JP 24116289 A JP24116289 A JP 24116289A JP H03104141 A JPH03104141 A JP H03104141A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- protrusions
- outside
- semiconductor device
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 229920005989 resin Polymers 0.000 claims abstract description 12
- 239000011347 resin Substances 0.000 claims abstract description 12
- 238000007789 sealing Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 13
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 238000005476 soldering Methods 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野コ 本発明は半導体装置の組立構造に関する。[Detailed description of the invention] [Industrial application fields] The present invention relates to an assembly structure of a semiconductor device.
［従来の技術コ
樹脂封止して組立が行われる半導体装置は、例えばクワ
ッドフラットパッケージ（ ＱＦＰ ）と呼ばれるタイ
プの場合、第２図のような構造をしている。すなわち、
タブ６上に工０チップ１をエポキシ系接着剤などで接合
し、パッド電極２とリード端子７とを金属細線５により
接続する。しかる後に樹脂封止して、半田メッキ等を行
った後でリード切断・成形を行って完成させるというも
のであった。[Conventional Technology] A semiconductor device that is assembled using resin sealing, for example, is of a type called a quad flat package (QFP), and has a structure as shown in FIG. That is,
The chip 1 is bonded onto the tab 6 using an epoxy adhesive or the like, and the pad electrode 2 and the lead terminal 7 are connected by a thin metal wire 5. After that, it was sealed with resin, solder plated, etc., and then the leads were cut and molded to complete the process.
［発明が解決しようとする課題コ
最近、電子機器の小型化への厳しい要求とあいまって、
半導体外形の小型化も急激に進んでいる例えば第２図に
示すＱ，ＩＦＦの場合も、樹脂封止部の外側のリード端
子のピッチは，’ｔｏ，ｎ．ｓ，Ｌ１．６５ｒｒａ等の
例からα５，ａ４，０．３ｍ等の例へと変化しており、
それに伴って樹脂封止部４のサイズも小型化して来てい
る。しかし、金属細線で接続する構造では工Ｏチップと
ほぼ同じサイズの半導体装置を製造しようとする場合、
限界にぶつかってしまう。[Problems to be solved by inventions] Recently, coupled with the strict demand for miniaturization of electronic devices,
For example, in the case of the Q, IFF shown in FIG. 2, where the size of semiconductors is rapidly becoming smaller, the pitch of the lead terminals outside the resin sealing part is 'to, n. It has changed from examples such as s, L1.65rra to α5, a4, 0.3m, etc.
Along with this, the size of the resin sealing portion 4 has also become smaller. However, when trying to manufacture a semiconductor device that is approximately the same size as an O-chip with a structure in which connections are made using thin metal wires,
I hit my limit.
本発明は゛上記の課題を解決すべくなされたもので、そ
の目的とするところは、ＩＣチップとほぼ同等のサイズ
の半導体装置を提供するところにある。The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a semiconductor device of approximately the same size as an IC chip.
［課題を解決するための手段コ
本発明の半導体装置は、ＩＣチップのパッド電極上に樹
脂封止部の外部へ突出する突起部が形成されている事を
特徴とする。[Means for Solving the Problems] The semiconductor device of the present invention is characterized in that a protrusion projecting to the outside of the resin sealing portion is formed on a pad electrode of an IC chip.
［実施例］ 第１図は本発明実施例の模式的断面図である。[Example] FIG. 1 is a schematic cross-sectional view of an embodiment of the present invention.
なお、前述の従来例と同一または相当部分には同じ符号
を付してある。Note that the same or equivalent parts as in the conventional example described above are given the same reference numerals.
本発明では、ＩＣチップ１のパクド電極２上に突起部３
を形成するが、これはウエハプロセスにおいてたとえば
半田バンブ形成と同様の方法で製造する事ができる。In the present invention, the protrusion 3 is provided on the padded electrode 2 of the IC chip 1.
This can be manufactured in a wafer process using a method similar to, for example, solder bump formation.
ＩＣ組立工程ではＩＣチップ１を突起部３が表面から外
餌に出るように樹脂封止すれば完成される。In the IC assembly process, the IC chip 1 is completed by sealing it with a resin so that the protrusion 3 protrudes from the surface.
基板実装時には、この突出部３をプリント基板上に形成
されたフットプリントに合せてリフローなどの方法によ
り半田づげすればよく、工０チップとほぼ同等の実装占
有面積が実現できる。When mounting on a board, the protrusion 3 may be soldered by a method such as reflow in accordance with the footprint formed on the printed board, and a mounting area approximately equivalent to that of a zero-process chip can be achieved.
ここでは、突起部の形成方法として半田バンプと同種の
方法を紹介したが、導電性の材料であれば他のものを使
用して形成してもよい。この場合、樹脂封止後に突起部
に半田メッキを施せば半田による突起部の場合と同様に
基板へ実装できる。Here, a method similar to that of solder bumps has been introduced as a method for forming protrusions, but other materials may be used as long as they are conductive. In this case, if the protrusion is plated with solder after resin sealing, it can be mounted on the board in the same way as in the case of the protrusion using solder.
［発明の効果］
以上述べた様に本発明によれば、ＩＣチップのパッド電
極上に樹脂封止部の外側へ突出する突起部が形成されて
いるので、ＩＣチクブとほぼ同等のサイズの半導体装置
をか提供でき、半導体装置の大幅な小型化と基板実装の
大幅な高密度化がはかられるという効果を有する。[Effects of the Invention] As described above, according to the present invention, a protrusion protruding to the outside of the resin sealing part is formed on the pad electrode of an IC chip, so that a semiconductor of approximately the same size as an IC chip is formed. This has the effect of significantly reducing the size of semiconductor devices and greatly increasing the density of board mounting.
第１図は、本発明の半導体装置の一実施例を示す模式的
断面図。第２図は、従来の半導体装置の模式的断面図で
ある。
・・・・・・・・・ＩＣチップ
・・・・・・・・・パッド電極
・・・・・・・・・突起部
・・・・・・・・・樹脂封止部
・・・・・・・・・金属細線
・・・・・・・・・タ ブ
・・・・・・・・・リード端子
以上FIG. 1 is a schematic cross-sectional view showing an embodiment of the semiconductor device of the present invention. FIG. 2 is a schematic cross-sectional view of a conventional semiconductor device.・・・・・・・・・IC chip・・・・・・・・・Pad electrode・・・・・・Protrusion・・・・・・Resin sealing part・・・・・・...Thin metal wire...Tab...Lead terminal or higher
Claims (1)
記ＩＣチップのパッド電極上には前記樹脂封止部の外部
へ突出する突起部が形成されている事を特徴とする半導
体装置。1. A semiconductor device comprising an IC chip sealed with resin, characterized in that a protrusion projecting to the outside of the resin sealing portion is formed on a pad electrode of the IC chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24116289A JPH03104141A (en) | 1989-09-18 | 1989-09-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24116289A JPH03104141A (en) | 1989-09-18 | 1989-09-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03104141A true JPH03104141A (en) | 1991-05-01 |
Family
ID=17070183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24116289A Pending JPH03104141A (en) | 1989-09-18 | 1989-09-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03104141A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5554887A (en) * | 1993-06-01 | 1996-09-10 | Mitsubishi Denki Kabushiki Kaisha | Plastic molded semiconductor package |
| US5656863A (en) * | 1993-02-18 | 1997-08-12 | Mitsubishi Denki Kabushiki Kaisha | Resin seal semiconductor package |
| US5925934A (en) * | 1995-10-28 | 1999-07-20 | Institute Of Microelectronics | Low cost and highly reliable chip-sized package |
| US6229222B1 (en) | 1998-06-09 | 2001-05-08 | Oki Electric Industry Co., Ltd. | Semiconductor device and method of fabricating the same |
-
1989
- 1989-09-18 JP JP24116289A patent/JPH03104141A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5656863A (en) * | 1993-02-18 | 1997-08-12 | Mitsubishi Denki Kabushiki Kaisha | Resin seal semiconductor package |
| US5753973A (en) * | 1993-02-18 | 1998-05-19 | Mitsubishi Denki Kabushiki Kaisha | Resin seal semiconductor package |
| US5920770A (en) * | 1993-02-18 | 1999-07-06 | Mitsubishi Denki Kabushiki Kaisha | Resin seal semiconductor package and manufacturing method of the same |
| US6191493B1 (en) | 1993-02-18 | 2001-02-20 | Mitsubishi Denki Kabushiki Kaisha | Resin seal semiconductor package and manufacturing method of the same |
| US5554887A (en) * | 1993-06-01 | 1996-09-10 | Mitsubishi Denki Kabushiki Kaisha | Plastic molded semiconductor package |
| US5710062A (en) * | 1993-06-01 | 1998-01-20 | Mitsubishi Denki Kabushiki Kaisha | Plastic molded semiconductor package and method of manufacturing the same |
| US5834340A (en) * | 1993-06-01 | 1998-11-10 | Mitsubishi Denki Kabushiki Kaisha | Plastic molded semiconductor package and method of manufacturing the same |
| US6046071A (en) * | 1993-06-01 | 2000-04-04 | Mitsubishi Denki Kabushiki Kaisha | Plastic molded semiconductor package and method of manufacturing the same |
| US5925934A (en) * | 1995-10-28 | 1999-07-20 | Institute Of Microelectronics | Low cost and highly reliable chip-sized package |
| US6229222B1 (en) | 1998-06-09 | 2001-05-08 | Oki Electric Industry Co., Ltd. | Semiconductor device and method of fabricating the same |
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