JPS6085475U - clamp circuit - Google Patents

clamp circuit

Info

Publication number
JPS6085475U
JPS6085475U JP17741683U JP17741683U JPS6085475U JP S6085475 U JPS6085475 U JP S6085475U JP 17741683 U JP17741683 U JP 17741683U JP 17741683 U JP17741683 U JP 17741683U JP S6085475 U JPS6085475 U JP S6085475U
Authority
JP
Japan
Prior art keywords
emitter
transistor
base
clamp circuit
whose
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17741683U
Other languages
Japanese (ja)
Other versions
JPH0113480Y2 (en
Inventor
纓坂　博
Original Assignee
クラリオン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クラリオン株式会社 filed Critical クラリオン株式会社
Priority to JP17741683U priority Critical patent/JPS6085475U/en
Publication of JPS6085475U publication Critical patent/JPS6085475U/en
Application granted granted Critical
Publication of JPH0113480Y2 publication Critical patent/JPH0113480Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のものの一例を示す回路図、第２．３図は
波形図、第４図はこの考案の一実施例を示す回路図であ
る。 １．１１：入力端子、２，１２：出力端子、３．１３：
コンデンサ、４，５，６：トランジスタ、７．１７：基
準電源、８．１８：抵抗、９：抵抗、２０：ダイオード
。FIG. 1 is a circuit diagram showing an example of a conventional device, FIGS. 2 and 3 are waveform diagrams, and FIG. 4 is a circuit diagram showing an embodiment of this invention. 1.11: Input terminal, 2,12: Output terminal, 3.13:
Capacitor, 4, 5, 6: Transistor, 7.17: Reference power supply, 8.18: Resistor, 9: Resistor, 20: Diode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力端子にコンデンサを介してベースが接続され、かつ
出力端子にエミッタが接続された第１トランジスタのエ
ミッタに、基準電源にエミッタが接続された第２トラン
ジスタのベースを接続し、第２トランジスタのコレクタ
と第１トランジスタのベースとに、エミッタホロワをな
す第３トランジスタを接続してなるクランプ回路。The emitter of a first transistor whose base is connected to the input terminal via a capacitor and whose emitter is connected to the output terminal is connected to the base of a second transistor whose emitter is connected to a reference power supply, and the collector of the second transistor is connected to the emitter of the first transistor whose base is connected to the input terminal via a capacitor and whose emitter is connected to the output terminal. A clamp circuit is formed by connecting a third transistor forming an emitter follower to the base of the first transistor.
JP17741683U 1983-11-18 1983-11-18 clamp circuit Granted JPS6085475U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17741683U JPS6085475U (en) 1983-11-18 1983-11-18 clamp circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17741683U JPS6085475U (en) 1983-11-18 1983-11-18 clamp circuit

Publications (2)

Publication Number Publication Date
JPS6085475U true JPS6085475U (en) 1985-06-12
JPH0113480Y2 JPH0113480Y2 (en) 1989-04-20

Family

ID=30385444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17741683U Granted JPS6085475U (en) 1983-11-18 1983-11-18 clamp circuit

Country Status (1)

Country Link
JP (1) JPS6085475U (en)

Also Published As

Publication number Publication date
JPH0113480Y2 (en) 1989-04-20

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