JPS5984417A - Iii-v family mixed crystalline semiconductor device - Google Patents
Iii-v family mixed crystalline semiconductor deviceInfo
- Publication number
- JPS5984417A JPS5984417A JP57193891A JP19389182A JPS5984417A JP S5984417 A JPS5984417 A JP S5984417A JP 57193891 A JP57193891 A JP 57193891A JP 19389182 A JP19389182 A JP 19389182A JP S5984417 A JPS5984417 A JP S5984417A
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- Prior art keywords
- layer
- substrate
- iii
- source
- mixed crystal
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02543—Phosphides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
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- Condensed Matter Physics & Semiconductors (AREA)
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- Chemical & Material Sciences (AREA)
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- Semiconductor Lasers (AREA)
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Abstract
Description
【発明の詳細な説明】
本発明は、１■−Ｖ族混晶半導体の気相エピタキシャル
成長において、基板と格子定数の異なるエピタキシャル
層を成長せしめようとする際、最初に基板の格子定数に
一致する組成かられずかづつ混晶組成を変化せしめるこ
とにより格子定数を変え、最終的に希望する格子定数を
有する組成の混晶に至ることが可能なグレーデツド層に
関するものである。DETAILED DESCRIPTION OF THE INVENTION In the vapor phase epitaxial growth of a 1■-V group mixed crystal semiconductor, when an epitaxial layer is grown whose lattice constant is different from that of a substrate, the lattice constant of the substrate is first matched to that of the substrate. The present invention relates to a graded layer in which the lattice constant can be changed by gradually changing the mixed crystal composition, and finally a mixed crystal having a desired lattice constant can be obtained.
ＩＩＩ −Ｖ族混晶半導体において、例えば、Ｉｎ−Ｇ
ａ −Ａｓ −Ｐ系では、禁制帯幅ＦｉＩｎＡｓの０．
３６ ｅ ＶがらＧａＰ ノ２．２５ｅＶまで、組成を
変化させることによって種々の禁制帯幅を有する混晶が
可能で、赤外領域から可視値域までレーザダイオード、
発光ダイオード、受光素子等光デバイスとして幅広い応
用が考えられる１、シかしながら、基板となるバルク結
晶は、ＩｎＰ、 ＧａＡｓ 、 ＧａＰ、 ＩｎＡｓの
２元化合物以外には作製することが非常に困難なために
、その上のエピタキシャル層もこれらの基板の格子定数
と一致する組成を有する結晶に限られていた。前述の４
元系混晶で言えば、ＩｎＰ基板を用いた場合には禁制帯
幅で０．７５ｅＶ 〜１．２８ｅＶ、 ＧａＡｓ基板を
用いた場合には１．４３ｅＶ〜１．８８ｅＶの混晶に限
られることになる。In III-V group mixed crystal semiconductors, for example, In-G
In the a-As-P system, the forbidden band width FiInAs is 0.
By changing the composition, it is possible to create mixed crystals with various forbidden band widths, from 36 eV to 2.25 eV for GaP.
It can be used in a wide range of applications as optical devices such as light emitting diodes and photodetectors1. However, bulk crystals that serve as substrates are extremely difficult to fabricate using materials other than binary compounds of InP, GaAs, GaP, and InAs. Therefore, the epitaxial layer thereon has also been limited to crystals having a composition matching the lattice constant of these substrates. 4 mentioned above
In terms of elemental mixed crystals, the forbidden band width is limited to 0.75 eV to 1.28 eV when using an InP substrate, and 1.43 eV to 1.88 eV when using a GaAs substrate. become.
この範囲を、従来容易に入手できる基板を用いて拡大す
ることを可能にした技術がグレーデツド層の導入である
。すなわち、格子定数が基板と大きく異なる結晶を基板
上に成長させた場合、その界面から多数の転位が導入さ
れ、結晶性が大きくそこなわれ、表面状態も悪化して実
用的な結晶を得ることがで唇ない。しかし、極めて格子
定数の差がわずかである場合（Δａ／ａ＜５Ｘ１０ 、
Δａ：基板の格子定数とその上に成長させようとする結
晶の格子定数の差、ａ：基板の格子定数）には転位の導
入も比較的少なく鏡面性の良いエピタキシャル層が成長
することを利用して、エピタ・Ｖシャル層の成長方向に
混晶の組成を変えることによって格子定数を少しづつ変
化させ、最終的に希望する格子定数の組成を有するエピ
タキシャル層を成長せしめることができる。また、が近
では、格子定数を成長方向に連続的に変えるのではな（
、階段的に変化させる方法が試みられている。これは、
格子定数を変化させた界面でミスフィツト転位が導入さ
れる程度に階段的に変化せしめるもので、この方法によ
ればミスフィツトの度合が適当であれば導入されたミス
フィツト転位は界面内にとどまり、エピタキシャル層の
成長方向に伝搬されることはな（、かつ、下地結晶から
のびてきた転位さえも一部をその界面で結晶の外に逃が
すことができる。このようにして入手容易な基板上に格
子定数の異なった高品質のエピタキシャル層を比較的容
易に成長することができるグレーデツド層技術は、今後
増々その応用範囲が広がることが期待できる。A technique that has made it possible to expand this range using conventionally easily available substrates is the introduction of graded layers. In other words, if a crystal whose lattice constant is significantly different from that of the substrate is grown on a substrate, a large number of dislocations will be introduced from the interface, the crystallinity will be greatly impaired, and the surface condition will deteriorate, making it difficult to obtain a practical crystal. No lips. However, when the difference in lattice constant is extremely small (Δa/a<5X10,
Δa: Difference between the lattice constant of the substrate and the lattice constant of the crystal to be grown on it; a: Lattice constant of the substrate) takes advantage of the fact that an epitaxial layer with good specularity is grown with relatively few introductions of dislocations. By changing the composition of the mixed crystal in the growth direction of the epitaxial/Vsial layer, the lattice constant is gradually changed, and finally an epitaxial layer having a desired lattice constant composition can be grown. Also, in the vicinity of , the lattice constant does not change continuously in the growth direction (
, a method of changing stepwise has been attempted. this is,
The lattice constant is changed stepwise to the extent that misfit dislocations are introduced at the interface. According to this method, if the degree of misfit is appropriate, the introduced misfit dislocations will remain within the interface and the epitaxial layer The dislocations are not propagated in the growth direction (and even some of the dislocations that have grown from the underlying crystal can escape to the outside of the crystal at the interface. In this way, the lattice constant can be Graded layer technology, which allows high-quality epitaxial layers of different types to be grown relatively easily, is expected to have a wider range of applications in the future.
ところで、従来はグレーデツド層として基板の構成元素
にＩＩＩ族およびＶ族元素のうちのいずれが＝ｆｉ類の
元素を加えた３元混晶が用いられてきた８例えば、Ｉｎ
−ＧａＡｓ −Ｐ系において、５．６λの格子定数を
有するエピタキシャル層を成長させようとした場合、基
板はＧａＰ （格子定数： ５．４５Ａ ＞を用いてグ
レーデツド層として、ＧａＰにＩｎもしくは八８を加え
た３元混晶を用いて、格子定数を変える方法が取られて
きた。ところで、このグレーテツド層として用いる３元
混晶は、ＩｎＧａＰを例にとると、下地結晶の格子との
ミスフィツトが０．０５％以下の場合には、成長面と平
行な格子はほぼ下地結晶の格子と整合し、垂直な方向の
格子定数が変化する弾性変形によっ【歪を緩和し転位を
生ずることな（成長する。しかし、それ以上ミスフィツ
トが大きくなると転位が発生する。一般に３元混晶にお
いては、後述する本発明の４元混晶に比較して転位の発
生し７ｊいミスフィツトのＷ［容範囲が狭く、連続的に
格子定数を変化させる場合には、組成を非常にゆっくり
と変化させる必要があり、かつ供給するガス流月を精密
に制御しなければならなかった、また、格子？数を階段
的に変化させる方法においては、意図的にミスフィツト
転位をだけ導入する必要があるが、３元混晶の場合には
この転位のみ薪曇ミ発生させるためには、組成のきわめ
て精密な制御が必要となり、現実には、エピタキシーデ
ル層の成長方向への転位が相当発生していた。By the way, in the past, a ternary mixed crystal was used as a graded layer in which an element of group III or V group = fi was added to the constituent elements of the substrate8. For example, In
-GaAs-P system, when trying to grow an epitaxial layer with a lattice constant of 5.6λ, the substrate is GaP (lattice constant: 5.45A) as a graded layer, and GaP is injected with In or 88 A method has been used to change the lattice constant by using an added ternary mixed crystal.By the way, in the case of InGaP, the ternary mixed crystal used as the graded layer has zero misfit with the lattice of the underlying crystal. When the lattice is less than .05%, the lattice parallel to the growth plane almost matches the lattice of the underlying crystal, and elastic deformation that changes the lattice constant in the perpendicular direction (relaxes strain and prevents the growth of dislocations) However, if the misfit becomes larger than that, dislocations will occur.In general, in a ternary mixed crystal, dislocations are less likely to occur in a ternary mixed crystal than in a quaternary mixed crystal of the present invention, which will be described later. When changing the lattice constant continuously, it was necessary to change the composition very slowly, and the gas flow to be supplied had to be precisely controlled. In this method, it is necessary to intentionally introduce only misfit dislocations, but in the case of ternary mixed crystals, extremely precise control of the composition is required in order to generate only these dislocations. In reality, a considerable number of dislocations occurred in the growth direction of the epitaxial del layer.
更に、最終的に得られたエピタキシャル層の表面状態は
、ミスフィツト転位の影響により、クロスハツチやライ
ンハツチパターンが見られデバイス作製上障害になるこ
とが多かった。Furthermore, the surface state of the finally obtained epitaxial layer has crosshatch and linehatch patterns due to the influence of misfit dislocations, which often poses an obstacle in device fabrication.
本発明は、このような従来の欠点を除去せしめて、転位
が少な（表面状態の良好なエピタキシャル層が形成でき
るグレーデツド層を提供することにある、
本発明によれば１］ｔ −Ｖ族半導体基板上に、階段状
あるいは連続的に組成が変化するグレーデツド層が設け
られ、該グレーデツド層上に前記半導体基板とは異なる
格子定数のＩＩＩ −Ｖ族混晶半導体エピタキシャル層
が設けられたｌｌ［−Ｖ族混晶半導体装置において、前
記グレーデツド層として４元以上のＩＩＩ −Ｖ族混晶
半導体エビクキシャル層を用いたことを特徴とするＩＩ
Ｉ −Ｖ族混晶半導体装置が得られる。The object of the present invention is to eliminate such conventional drawbacks and provide a graded layer with few dislocations (an epitaxial layer with good surface condition can be formed). According to the present invention, 1) t-V group semiconductor A graded layer whose composition changes stepwise or continuously is provided on the substrate, and a III-V group mixed crystal semiconductor epitaxial layer having a lattice constant different from that of the semiconductor substrate is provided on the graded layer. A group V mixed crystal semiconductor device, characterized in that the graded layer is a quaternary or more III-V group mixed crystal semiconductor evictional layer.
An IV group mixed crystal semiconductor device is obtained.
例えばＩｎＧａＡＩＩＰ ４元混晶においては、下地結
晶と異なる格子定数を有する組成のエピタキシャル層を
成長せしめる際、そのミスフィツトが０．３％以内であ
れば、転位を発生することな（鏡面性の良い結晶が成長
する。この範囲は前述の３元混晶のＩ ｎＧａＰに比較
しておよそ４倍程度大きなものである。多元混晶の場合
、下地結晶と格子定数が異なる結晶を成長せしめようと
する時、成長面と平行な格子はほぼ下地結晶の格子と整
合し、垂直方向の格子定数が変化することによって歪を
緩和しながら結晶が成長することはすでに述べたが、構
成元素が多くなると、格子点の元素の入れかえの自由度
が増加しより大きな歪に対しても対処できるものと考え
られる。そこで、４元以上の多元混晶をグレーデツド層
として用いることにより、組成を連続的に変化させる場
合においては、３元混晶のように、供給するガス流量を
精密に制御して、組成をゆっくりと変化させる必要がな
（なり、その形成が容易になる。また、格子定数を階段
的に変化させる場合におし・ては、そのステップ数を３
元混晶を用いる場合の１７４程度にすることができ、こ
れに伴い、成長方向にのびる転位も減らずことができる
。更に、８元混晶を用いた場合には、成長表面上に、ミ
スフィツト転位に対応してラインハツチやクロスハツチ
パターンが観察されるが、４元以上の混晶を用いること
によって、鏡面性にすぐれた成長層を得ることができる
。For example, in InGaAIIP quaternary mixed crystal, when growing an epitaxial layer with a composition that has a different lattice constant from that of the underlying crystal, if the misfit is within 0.3%, dislocations will not occur (crystal with good specularity). This range is about four times larger than that of the ternary mixed crystal InGaP mentioned above.In the case of a multi-component mixed crystal, when trying to grow a crystal with a lattice constant different from that of the underlying crystal, As already mentioned, the lattice parallel to the growth plane almost matches the lattice of the underlying crystal, and the crystal grows while relaxing the strain by changing the lattice constant in the vertical direction. However, as the number of constituent elements increases, the lattice changes. It is thought that the degree of freedom in replacing elements at a point increases and it is possible to cope with larger strains.Therefore, by using a multi-component mixed crystal of quaternary or higher elements as a graded layer, it is possible to continuously change the composition. Unlike ternary mixed crystals, it is not necessary to precisely control the gas flow rate to slowly change the composition (this makes it easier to form). If you want to do this, increase the number of steps to 3.
The number can be reduced to about 174 when using an original mixed crystal, and accordingly, dislocations extending in the growth direction can also be reduced. Furthermore, when an 8-element mixed crystal is used, line hatch or cross-hatch patterns are observed on the growth surface corresponding to misfit dislocations, but by using a quaternary or higher mixed crystal, excellent specularity is obtained. A grown layer can be obtained.
次に本発明を実施例に基づき、図を参照しながら詳述す
る。Next, the present invention will be explained in detail based on examples and with reference to the drawings.
実施例
本発明を用いてＧａＡａ基板上にＩｎＧａＡｓＰグンー
デッド層を成長させた例について＠１図〜第２図を用い
て説明する。本実施例はハイドライド気相成長法を用い
ており、成長装置の概略図を第１図に示す。この成長装
置は上流部分が２つの成長室１．２にわかれており、そ
れぞれの成長室でＩｎＧａＡｓＰ系混晶の成長が用能で
ある。基板３は、各成長室の出口に近接１〜て設置し、
基板ホルダー４を回転することにより、約１秒で成長室
間を移動できる。EXAMPLE An example of growing an InGaAsP grounded layer on a GaAa substrate using the present invention will be described with reference to FIGS. 1 and 2. This example uses the hydride vapor phase growth method, and a schematic diagram of the growth apparatus is shown in FIG. The upstream portion of this growth apparatus is divided into two growth chambers 1.2, each of which is capable of growing an InGaAsP-based mixed crystal. The substrate 3 is placed close to the exit of each growth chamber,
By rotating the substrate holder 4, it can be moved between growth chambers in about 1 second.
温度は上流のＩＪＩ族金岡ソース部を８００℃、基板部
を７５０℃に設定した。基板３としてはＧａＡｓ（１０
０）面を用い、反応管にセットした後上段の成長室１で
導入管５よりＡｄＩ３ガスを供給（７ながら昇温した。The temperature was set at 800°C for the upstream IJI group Kanaoka source part and 750°C for the substrate part. The substrate 3 is GaAs (10
After setting the reaction tube in the reaction tube using the 0) surface, AdI3 gas was supplied from the introduction tube 5 in the upper growth chamber 1 (the temperature was raised at 7).
設定温度に到達した後、下段の成長室２のＩｎソース６
、Ｇａソース７上にＨＣＩガス、導入管８よりＡ８Ｈ３
、ＰＨｓガスを供給しＩｎｏ２ｓ Ｇａｏ、ｙｔ Ａｌ
２Ｏ，４Ｉ Ｐｏ、５９ 混晶が成長する条件に設定し
た。これはほぼＧａＡｓに格子整合する４元混晶である
。基板を下段の成長室に移して成長を開始すると同時に
上段の成長室１をＩｎｏ、ｚ５Ｇａｏ、７ｓ Ａｇ３．
４１ Ｐｏ、５９ の４元混晶が成長するように、Ｉｎ
ソース８、Ｇａソース９上の１■Ｃノガス、および導入
管５より供給するＡ、ｓ Ｈ３、ＰＨ３ガス流量を設定
する。下段の成長室２で約５μｍの厚さのＩｎｏ２９（
’ｙａｏ７＋ Ａ８ｏ４．ｓ ＰＯ５９エピタキシャル
層を成長した後、基板を上段の成長室１に移動する。こ
の上うに一方の成長室で成長を行な−、ている間に、も
う一方の成長室で次の成長の壁倫を行なうことにより連
続的に次表のような階段的な格子定数の変化を南するグ
レーデツド層の成長を行〕ｊ゛つた。After reaching the set temperature, the In source 6 in the lower growth chamber 2
, HCI gas on Ga source 7, A8H3 from inlet pipe 8
, PHs gas was supplied and Ino2s Gao, yt Al
Conditions were set to allow the growth of 2O,4IPo,59 mixed crystals. This is a quaternary mixed crystal that is approximately lattice matched to GaAs. The substrate is transferred to the lower growth chamber to start growth, and at the same time, the upper growth chamber 1 is filled with Ino, z5Gao, 7s Ag3.
In order to grow a quaternary mixed crystal of 41 Po, 59
The flow rates of the 1■C gas on the source 8, the Ga source 9, and the A, sH3, and PH3 gases supplied from the introduction pipe 5 are set. Ino29 (about 5 μm thick) was grown in the lower growth chamber 2.
'yao7+ A8o4. After growing the s PO59 epitaxial layer, the substrate is moved to the upper growth chamber 1. Furthermore, growth is performed in one growth chamber, and while the next growth is performed in the other growth chamber, the lattice constant changes continuously in a stepwise manner as shown in the table below. A graded layer grew to the south.
この表において下地結晶とのミスフィツトとは例えば１
５番の層における値は１４番の層との間のミスフィツト
を示す。階段的な格子定数の変化によってその界面には
ミスフィツト転位が導入され歪が緩和される。しかし、
Ｈ，長方向への転位は導入さｈｌ（いことがｆＪに長表
面のエッチピットの観１察から明らかになった。基板１
１として用いたＧａＡｓは転位に対応するエッチピット
密度が２０００個／ｄのものを用いたが、成長後の表面
では７００個／ｄに減少し′〔いた。これケよつまり新
たな転位の導入がないばかりか、逆にこのようなグレー
デツド層は転位を減少させる効果を持つことが明らかと
なった。更に表面も干渉顕微鏡で観察した結果、はとん
ど凹凸のない良好なもので、本発明に依る方法は、この
−ヒに例えばダブルへテロレーザ構造を形成する上で非
常に有用性の高い方法であること 、−が明らかとな
った。In this table, the misfit with the underlying crystal is, for example, 1
The value at layer number 5 indicates the misfit with layer number 14. Misfit dislocations are introduced at the interface due to the stepwise change in the lattice constant, and the strain is relaxed. but,
H, dislocations in the long direction were introduced into fJ, which became clear from the observation of etch pits on the long surface of substrate 1.
The GaAs used as No. 1 had an etch pit density of 2000 pits/d corresponding to dislocations, but this decreased to 700 pits/d on the surface after growth. Not only does this mean that no new dislocations are introduced, but on the contrary, it has become clear that such graded layers have the effect of reducing dislocations. Furthermore, as a result of observing the surface using an interference microscope, it was found that the surface had almost no irregularities, and the method according to the present invention is a highly useful method for forming, for example, a double hetero laser structure on this surface. It became clear that -.
本実施例ではＩｎＧａＡｓＰ ４元混晶を例にとって説
明したが、１１１族とＶ族との組合わせによる他の４元
あるいは、それ以上の元素を含む混晶においても、その
原理から言って同様な結果を得られることは明らかであ
る。In this example, the InGaAsP quaternary mixed crystal was explained as an example, but the principle is similar for mixed crystals containing other quaternary elements or more elements such as a combination of group 111 and V group. It is clear that you can get results.
まｌこ本実ｔｊｉｌｊ例において、４元混晶をハイドラ
イド気相成長法を用いて成長させたが、他の成長法例え
ばＭｉ法、１ＩＩｉＯｃＶＤ法等を用いても同様の効果
がある。In the Makomoto example, the quaternary mixed crystal was grown using the hydride vapor phase epitaxy method, but the same effect can be obtained using other growth methods such as the Mi method and the 1IIIiOcVD method.
第１図は本発明の実施例に用いた２成長尾法によるハイ
ドライド気相成長装置の概略を示した図で、図中、１．
２が２つにわかれた成長章、３は基板、−１１１基仮ホ
ルダー、５．８はＡ３１１３、Ｐ）１３およびＨ２ガス
の導入管、６．８１ｊ）ｎソース、７．９はＧａンース
第２図は実り伽例で成長したエビクキシャツｌ；層の断
面構造を構成的に表わした図で、１０はＧａ Ａｓ基板
結晶、１１はＧａ Ａｓの格子に整合したＩｎＧａＡｓ
Ｐ エピタキシャル層、１２〜１５は格子定数を階段的
にづらし°〔成長したＩｎＧａＡｓＰエピタキシャルＭ
ｔ示す。FIG. 1 is a diagram schematically showing a hydride vapor phase growth apparatus using a two-growth tail method used in an example of the present invention.
2 is a growth chapter divided into two parts, 3 is a substrate, -111 group temporary holder, 5.8 is A3113, P) 13 and H2 gas introduction tube, 6.81j) n source, 7.9 is Ga source number Figure 2 is a diagram showing the cross-sectional structure of the layer grown in a fruitful example; 10 is a GaAs substrate crystal, and 11 is an InGaAs layer that matches the GaAs lattice.
P epitaxial layers 12 to 15 have their lattice constants changed stepwise [Grown InGaAsP epitaxial M
Show t.
Claims (1)
′が変化するグレーデツド層が設けられ、該グレーデツ
ド層上に前記半導体基板とは異なる格子定数の■−ｖ族
混晶半導体エピタキシャル層が設けられたＩＩＩ −Ｖ
族混晶半導体装置において、前記グレーデツド層として
４元以上のＩＩＩ −Ｖ族混晶半導体エピタキシャル層
を用いたことを特徴とするＩＩＩ −Ｖ族混晶半導体装
置。A graded layer whose composition changes in a stepwise or continuous manner is provided on a ■-V group semiconductor substrate, and a ■-V group mixed crystal semiconductor epitaxial layer having a lattice constant different from that of the semiconductor substrate is formed on the graded layer. III-V provided
A group III-V mixed crystal semiconductor device, characterized in that a quaternary or higher group III-V mixed crystal semiconductor epitaxial layer is used as the graded layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57193891A JPS5984417A (en) | 1982-11-04 | 1982-11-04 | Iii-v family mixed crystalline semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57193891A JPS5984417A (en) | 1982-11-04 | 1982-11-04 | Iii-v family mixed crystalline semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5984417A true JPS5984417A (en) | 1984-05-16 |
Family
ID=16315454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57193891A Pending JPS5984417A (en) | 1982-11-04 | 1982-11-04 | Iii-v family mixed crystalline semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5984417A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01194352A (en) * | 1988-01-28 | 1989-08-04 | Fujitsu Ltd | Photo detector and integrated receiver |
| JPH04132270A (en) * | 1990-09-25 | 1992-05-06 | Mitsui Mining & Smelting Co Ltd | Semiconductor photodetector |
| JP2019201091A (en) * | 2018-05-16 | 2019-11-21 | 住友電気工業株式会社 | Semiconductor laminate and light receiving element |
-
1982
- 1982-11-04 JP JP57193891A patent/JPS5984417A/en active Pending
Non-Patent Citations (1)
| Title |
|---|
| APPL.PHYS.LETT.=1975 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01194352A (en) * | 1988-01-28 | 1989-08-04 | Fujitsu Ltd | Photo detector and integrated receiver |
| JPH04132270A (en) * | 1990-09-25 | 1992-05-06 | Mitsui Mining & Smelting Co Ltd | Semiconductor photodetector |
| JP2019201091A (en) * | 2018-05-16 | 2019-11-21 | 住友電気工業株式会社 | Semiconductor laminate and light receiving element |
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