JPS62238618A - Semiconductor wafer - Google Patents
Semiconductor waferInfo
- Publication number
- JPS62238618A JPS62238618A JP8313586A JP8313586A JPS62238618A JP S62238618 A JPS62238618 A JP S62238618A JP 8313586 A JP8313586 A JP 8313586A JP 8313586 A JP8313586 A JP 8313586A JP S62238618 A JPS62238618 A JP S62238618A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- intermediate layer
- gap
- inp
- phosphorus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 claims description 12
- 239000002052 molecular layer Substances 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract description 3
- 230000005587 bubbling Effects 0.000 abstract description 2
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 40
- 238000000034 method Methods 0.000 description 12
- 150000001875 compounds Chemical class 0.000 description 11
- 239000013078 crystal Substances 0.000 description 11
- 235000012431 wafers Nutrition 0.000 description 8
- 229910005540 GaP Inorganic materials 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- UJXZVRRCKFUQKG-UHFFFAOYSA-K indium(3+);phosphate Chemical compound [In+3].[O-]P([O-])([O-])=O UJXZVRRCKFUQKG-UHFFFAOYSA-K 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 1
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
ウムＯリン（ＩｎＰ）結晶を得るための半導体ウェハ構
造に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor wafer structure for obtaining an InP crystal.
〈従来の技術〉
■−ｖ族化合物半導体は、光学的及び電気的特性に於い
て、■族元素半導体（Ｓ ｉ＋ Ｇ ｅ ）等では得ら
れない特徴を有しており、その特徴デバイスとしてＬＥ
Ｄ（発光ダイオード）、ＬＤ（レーザダイオード）等の
ＥＬ（エレクトロ・ルミネッセンス）デバイスや高速Ｆ
ＥＴ、ガン・ダイオード。<Prior art> ■-V group compound semiconductors have optical and electrical properties that cannot be obtained with group ■ element semiconductors (S i + G e ), etc., and LE is used as a characteristic device.
EL (electroluminescence) devices such as D (light emitting diode) and LD (laser diode) and high-speed F
ET, Gunn diode.
ホール素子等の電子デバイスが挙げられる。従来、この
ようなデバイスは■−ｖ族化合物半導体（ＧａＡｓ。Examples include electronic devices such as Hall elements. Conventionally, such devices are made of ■-v group compound semiconductors (GaAs.
ＩｎＰ、ＧａＰ等）の結晶基板上にエピタキシャル成長
等のプロセスを施して作製したものであり、■−Ｖ族化
合物半導体のバルク結晶が常に必要となる。しかしなが
ら、このよりな■−ｖ族化合物半導体のバルク結晶は、
結晶成長の困難さ等の為、歩留りが悪く、価格としても
非常に高価なものである。また、その他の問題点として
、バルク結晶のへき関しやすさが挙げられ、デバイス作
製プロ形状に於いても現在までのところ２〜３インチ形
状のものしか得られていなく、大面積化についても困難
な状態である。また、今後、高機能デバイスとして、三
次元回路素子や機能分離型デバイス（信号受発部を■−
■化合物が信号処理部をシリコン（Ｓｉ）が受は持って
いるようなデバイス）の開発を考慮した場合についても
、安価で良質のシリコン（Ｓｉ）単結晶基板上に■−ｖ
族化合物を形成することや、更にシリコン（Ｓｉ）と■
−ｖ族化合物との間に絶縁層を介して電気的に下層と上
層を素子分離することは重要な半導体素子形成技術であ
る。It is manufactured by performing a process such as epitaxial growth on a crystal substrate of (InP, GaP, etc.), and a bulk crystal of a ■-V group compound semiconductor is always required. However, this bulk crystal of the ■-v group compound semiconductor is
Due to the difficulty of crystal growth, the yield is low and the price is very high. In addition, another problem is the ease with which bulk crystals are separated, and even in the case of professional shapes for device fabrication, only 2 to 3 inch shapes have been obtained so far, making it difficult to increase the area. It is in a state of In addition, in the future, we will develop three-dimensional circuit elements and functionally separated devices (signal receiving and transmitting parts) as highly functional devices.
■ Even when considering the development of a device in which a compound has a signal processing part in silicon (Si), it is possible to
It is possible to form group compounds, and also to form compounds with silicon (Si).
It is an important semiconductor element formation technique to electrically isolate the lower layer and the upper layer through an insulating layer between the -v group compound and the lower layer and the upper layer.
〈発明が解決しようとする問題点〉
しかし、シリコン（Ｓｉ）基板上にインジウム・リンの
エピタキシャル成長を行なう場合には、その間に約８チ
の格子不整合によるエピタキシャル成長の困難さや格子
欠陥の発生及び単原子結晶上に２原子化合物を成長させ
る問題点としてアンチフェイズ・ドメインの発生があり
、良好な結晶成長を困難にしている。<Problems to be Solved by the Invention> However, when performing epitaxial growth of indium phosphide on a silicon (Si) substrate, there are difficulties in epitaxial growth due to lattice mismatch of about 8 inches, generation of lattice defects, and A problem with growing diatomic compounds on atomic crystals is the occurrence of antiphase domains, which makes it difficult to grow the crystals well.
本発明は、上記の点に鑑みて創案されたものであり、上
述のシリコン（Ｓｉ）単結晶基板への■−Ｖ族化合物半
導体成長法の一手法として、超薄膜形成を可能にする有
機金属熱分解法ＣＭＯＣＶＤ法）またはハライドＶＰＥ
法、更には分子線エピタキシャル成長法ＣＭＢＥ法）等
の成長法により、シリコン（Ｓｉ）単結晶基板上に良質
なインジウム・リン（Ｉ ｎＰ）のエピタキシャル成長
を行なうのに適した構造の半導体ウェハを提供すること
を目的としている。The present invention was devised in view of the above points, and is a method for growing a ■-V group compound semiconductor on the silicon (Si) single crystal substrate described above, using an organic metal that enables the formation of an ultra-thin film. thermal decomposition method (CMOCVD method) or halide VPE
To provide a semiconductor wafer with a structure suitable for epitaxial growth of high-quality indium phosphide (InP) on a silicon (Si) single crystal substrate by a growth method such as a molecular beam epitaxial growth method or a molecular beam epitaxial growth method (CMBE method). The purpose is to
く問題点を解決するための手段〉
上記の目的を達成するため、本発明の半導体ウニ／’ｄ
、シリコン（Ｓｉ）基板上に、ガリウム・リン（ＧａＰ
）及びガリウム・リン（ＧａＰ）とインジウム・リン（
Ｉ ｎＰ）の極薄膜交互成長層（超格子層）を含む中間
層を有し、この中間層上にインジウム・リン（Ｉ ｎＰ
）のエピタキシャル成長層を有するように構成している
。Means for Solving the Problems> In order to achieve the above object, the semiconductor unit/'d of the present invention
, gallium phosphide (GaP) on a silicon (Si) substrate.
) and gallium phosphide (GaP) and indium phosphide (
It has an intermediate layer including ultra-thin alternating growth layers (superlattice layer) of Indium Phosphate (InP), and on this intermediate layer
) has an epitaxial growth layer.
即ち、本発明はシリコン（Ｓｉ）基板とインジウム・リ
ン（Ｉｎｋ）エピタキシャル層との間に中間層として、
シリコン（Ｓｉ）とガリウム・リン（ＧａＰ）が格子整
合しやすいという事実（格子不整、約０．４係）に基づ
く積層構造を形成し、この中間層上にインジウム・リン
（ＩｎＰ）のエピタキシャル層を形成するように構成し
たものであり、シリコン（Ｓｉ）基板上にインジウム・
リン（ＩｎＰ）のエピタキシャル成長を行なう場合、緩
衝層としてガリウム・リン（ＧａＰ）及びインジウム・
リン（ＩｎＰ）とガリウム・リン（ＧａＰ）の超格子層
弁に実施態様として分子層レベルの膜厚で制御成長され
た超格子層（単分子層超格子）を用いることにより、良
質のインジウム・リン（ＩｎＰ）エピタキシャル層を形
成するようにしたものである。That is, the present invention provides an intermediate layer between a silicon (Si) substrate and an indium phosphide (Ink) epitaxial layer.
A stacked structure is formed based on the fact that silicon (Si) and gallium phosphide (GaP) are easily lattice matched (lattice mismatch, approximately 0.4 coefficient), and an epitaxial layer of indium phosphide (InP) is formed on this intermediate layer. It is structured to form indium on a silicon (Si) substrate.
When performing epitaxial growth of phosphorus (InP), gallium phosphide (GaP) and indium phosphorus (GaP) are used as a buffer layer.
By using a controlled-grown superlattice layer (monolayer superlattice) with a film thickness on the molecular layer level as an embodiment of the phosphorus (InP) and gallium phosphide (GaP) superlattice layer valve, high-quality indium A phosphorus (InP) epitaxial layer is formed.
〈実施例〉 以下、実施例に基づいて本発明の詳細な説明する。<Example> Hereinafter, the present invention will be described in detail based on Examples.
第１図は、本発明の一実施例の半導体ウェハの構造を示
す断面図である。FIG. 1 is a sectional view showing the structure of a semiconductor wafer according to an embodiment of the present invention.
第１図において、１はシリコン（Ｓｉ）単結晶基板であ
り、この基板１上に中間層２としてガリウム・リン層を
数十〜数百への膜厚に形成し、このガリウム拳リン（Ｇ
ａＰ）中間層２上にインジウム・リン（ＩｎＰ）とガリ
ウム・リン（ＧａＰ）の超格子層３を形成し、この超格
子層３上に、エピタキシャル成長によりインジウム・リ
ン（ＩｎＰ）層４を形成するように構成している。In FIG. 1, reference numeral 1 denotes a silicon (Si) single crystal substrate, on which a gallium phosphorus layer is formed as an intermediate layer 2 to a thickness of several tens to hundreds of layers.
aP) A superlattice layer 3 of indium phosphide (InP) and gallium phosphide (GaP) is formed on the intermediate layer 2, and an indium phosphide (InP) layer 4 is formed on this superlattice layer 3 by epitaxial growth. It is configured as follows.
次に、第１図に示した半導体ウェハ構造を作製するため
の作製条件及び形成法について説明する。Next, the manufacturing conditions and formation method for manufacturing the semiconductor wafer structure shown in FIG. 1 will be explained.
形成法としては、急峻なガス切り換えを実現するように
改造された横型ＭＯＣＶＤ装置を用いた方法による。形
成条件としては、反応室圧を５０〜１００ Ｔｏｒｒ
とし、原料ガスとしてＴＥＧａ（トリエチルガリウム）
、ＴＭＩｎ（トリメチル・インジウム）、ＰＨ，を用い
、Ｓ ｉＣＪ！コートしたグラファイト・サセプタ上に
シリコン（Ｓｉ）基板１を支持して高周波加熱を行ない
、原料ガスを熱分解して得られたものを基板上に堆積さ
せる。The formation method is a method using a horizontal MOCVD apparatus modified to realize abrupt gas switching. The formation conditions include a reaction chamber pressure of 50 to 100 Torr.
and TEGa (triethyl gallium) as the raw material gas.
, TMIn (trimethyl indium), PH, and SiCJ! A silicon (Si) substrate 1 is supported on a coated graphite susceptor and subjected to radio frequency heating to thermally decompose the raw material gas and deposit the resulting material on the substrate.
シリコン（Ｓｉ）基板１としては（１００）及び〔１１
０３方向に２〜５傾いた基板表面方位を有するものを用
い、成長装置へ基板１を導入するに先立ち、５％ＨＦ（
水溶液）によるエツチング及び水洗等の表面洗浄を行な
ったものを用いる。As the silicon (Si) substrate 1, (100) and [11
Using a substrate whose surface orientation is tilted 2 to 5 in the 03 direction, before introducing the substrate 1 into the growth apparatus, 5% HF (
Use materials that have undergone surface cleaning such as etching with an aqueous solution and washing with water.
上記の表面前処理後の基板１をＭＯＣＶＤ装置内サセプ
タに装填後、ＰＨ８（５０％ Ｈ２稀釈）及びＨ２を総
流量で６〜７ＳＬＭ流しながら１０００℃までサセプタ
温度を上昇させた後、その温度にて１０分間熱処理を行
なう。その後、温度を６５０〜７００℃に下げた状態に
てＴＥＧａ及びＰＨ３、更にはＨ２を同時に導入し、総
流量６〜７ＳＬＭにて１００〜２００Ａ／ｍｉｎの成長
速度で約５０〜１００ＡのＧａＰ層２を形成する（第１
層）。更に、第２中間層３として、ＩｎＰとＧａＰの超
格子層の成長では、第１層と同じＰＨＢ流景及び総流量
に固定し、夫々ＩｎＰではＴ Ｍ Ｉ ｎ ＋ Ｇ ａ
ＰではＴＥＧａへのバブリングＨ２ガス供給量を調整
することにより、ρ６０Ａ／ｍｉｎの成長速度にて３〜
９ｓｅｃ 間隔で、ＴＭＩｎとＴＥＧａのリアクターへ
のガス導入切り換えを行なうことにより、ＩｎＰとＧａ
Ｐの超格子層を１０００〜２００ＯＡ形成する。更に第
３層として前述と同様にＰＨ３流量及び総流量を固定し
、成長速度が２００〜３００Ａ／ｍｉｎ となるよう
にＴＭＩｎへのＨ２ガス供給量を設定することにより、
１〜２μｍのＩｎＰエピタキシャル層４を実現する。After loading the substrate 1 after the above surface pretreatment into the susceptor in the MOCVD apparatus, the susceptor temperature was raised to 1000 °C while flowing PH8 (50% H2 dilution) and H2 at a total flow rate of 6 to 7 SLM, and then the temperature was increased to that temperature. Heat treatment is performed for 10 minutes. Thereafter, while lowering the temperature to 650-700°C, TEGa, PH3, and H2 were simultaneously introduced, and a GaP layer 2 of approximately 50-100A was grown at a growth rate of 100-200A/min at a total flow rate of 6-7SLM. (first
layer). Furthermore, when growing a superlattice layer of InP and GaP as the second intermediate layer 3, the same PHB flow rate and total flow rate as the first layer are fixed, and T M I n + Ga for InP, respectively.
In P, by adjusting the amount of bubbling H2 gas supplied to TEGa, the growth rate is 3~60A/min.
By switching the gas introduction to the TMIn and TEGa reactors at 9 sec intervals, InP and Ga
A P superlattice layer of 1000 to 200 OA is formed. Furthermore, as the third layer, by fixing the PH3 flow rate and the total flow rate as described above and setting the H2 gas supply amount to TMIn so that the growth rate is 200 to 300 A/min,
An InP epitaxial layer 4 with a thickness of 1 to 2 μm is realized.
得られたＩｎＦ’ｏｎＳｉの表面は平坦で、光学顕微鏡
観察によっても鏡面成長が確認でき、クラック等の発生
もほとんど観られず、かなり良好なエピタキシャル層が
得られていることが確認された。The surface of the obtained InF'onSi was flat, specular growth was confirmed by optical microscope observation, and almost no cracks were observed, confirming that a fairly good epitaxial layer was obtained.
なお、ＩｎＰとＧａＰの超格子層膜厚やＧａＰの成長層
膜厚については、各種条件を変えることにより、より良
好な特性を有した半導体ウェハを得ることも可能である
。Note that by changing various conditions regarding the thickness of the InP and GaP superlattice layers and the thickness of the GaP growth layer, it is possible to obtain a semiconductor wafer with better characteristics.
また、このような半導体ウェハの作製については、ＭＯ
ＣＶＤ法に限らずＭＢＥ（分子線エピタキシー法）に於
いても同様に実施することが出来る。In addition, regarding the production of such semiconductor wafers, MO
Not only the CVD method but also MBE (molecular beam epitaxy) can be used in the same manner.
〈発明の効果〉
以上詳細に説明したように、本発明に係る中間層構造の
半導体ウェハを用いることにより、シリコン（Ｓ ｉ）
基板上への良好なインジウム・リン（ＩｎＰ）成長が可
能となり、例えばシリコン（Ｓｉ）基板として４〜６イ
ンチ形状を用いることにより、更に大面積でしかも低価
格のインジウム・リン（ＩｎＰ）基板の供給や機能分割
型デバイス及びシリコン（Ｓｉ）集積回路と化合物半導
体集積回路の組合せによる多機能高集積化等の複合化デ
バイス実現等に於いて非常に有用なるものである。<Effects of the Invention> As explained in detail above, by using the semiconductor wafer with the intermediate layer structure according to the present invention, silicon (Si)
Good indium phosphide (InP) can be grown on the substrate. For example, by using a 4- to 6-inch silicon (Si) substrate, it is possible to grow a larger area and lower cost indium phosphide (InP) substrate. It is very useful in the realization of complex devices such as multifunctional and highly integrated devices by supplying and functionally divided devices and by combining silicon (Si) integrated circuits and compound semiconductor integrated circuits.
第１図は本発明の一実施例の半導体ウェハの構造を示す
断面図である。
１・・・シリコン（Ｓｉ）基板、２・・・ガリウム・リ
ン（Ｇａｐ）中間層、３・・・インジウム・リン（Ｉｎ
Ｐ）とガリウム・リン（ＧａＰ）の超格子層、４・・・
インジウム・リン（ＩｎＰ）エピタキシャル成長層。FIG. 1 is a sectional view showing the structure of a semiconductor wafer according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Silicon (Si) substrate, 2...Gallium phosphide (Gap) intermediate layer, 3...Indium phosphide (In
P) and gallium phosphide (GaP) superlattice layer, 4...
Indium phosphide (InP) epitaxial growth layer.
Claims (1)
（ＧａＰ）中間層と、 該ガリウム・リン（ＧａＰ）中間層上に形成されたガリ
ウム・リン（ＧａＰ）とインジウム・リン（ＩｎＰ）の
超格子中間層と、 該超格子中間層上に形成されたインジウム・リン（Ｉｎ
Ｐ）エピタキシャル成長層と を有してなることを特徴とする半導体ウェハ。 ２、前記超格子中間層は分子層厚の膜厚にて制御された
極薄膜交互成長層で構成してなることを特徴とする特許
請求の範囲第１項記載の半導体ウェハ。[Claims] 1. A silicon (Si) substrate, a gallium phosphide (GaP) intermediate layer formed on the silicon (Si) substrate, and a gallium phosphide (GaP) intermediate layer formed on the gallium phosphide (GaP) intermediate layer. A superlattice intermediate layer of gallium phosphide (GaP) and indium phosphide (InP), and an indium phosphide (InP) formed on the superlattice intermediate layer.
P) A semiconductor wafer comprising an epitaxial growth layer. 2. The semiconductor wafer according to claim 1, wherein the superlattice intermediate layer is composed of extremely thin alternately grown layers whose thickness is controlled to be a molecular layer thickness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8313586A JPS62238618A (en) | 1986-04-09 | 1986-04-09 | Semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8313586A JPS62238618A (en) | 1986-04-09 | 1986-04-09 | Semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62238618A true JPS62238618A (en) | 1987-10-19 |
Family
ID=13793756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8313586A Pending JPS62238618A (en) | 1986-04-09 | 1986-04-09 | Semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62238618A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5016065A (en) * | 1988-11-04 | 1991-05-14 | Sharp Kabushiki Kaisha | Compound semiconductor substrate with InGaP layer |
| US6419742B1 (en) * | 1994-11-15 | 2002-07-16 | Texas Instruments Incorporated | method of forming lattice matched layer over a surface of a silicon substrate |
-
1986
- 1986-04-09 JP JP8313586A patent/JPS62238618A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5016065A (en) * | 1988-11-04 | 1991-05-14 | Sharp Kabushiki Kaisha | Compound semiconductor substrate with InGaP layer |
| US6419742B1 (en) * | 1994-11-15 | 2002-07-16 | Texas Instruments Incorporated | method of forming lattice matched layer over a surface of a silicon substrate |
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