JPH01194352A - Photo detector and integrated receiver - Google Patents
Photo detector and integrated receiverInfo
- Publication number
- JPH01194352A JPH01194352A JP63018391A JP1839188A JPH01194352A JP H01194352 A JPH01194352 A JP H01194352A JP 63018391 A JP63018391 A JP 63018391A JP 1839188 A JP1839188 A JP 1839188A JP H01194352 A JPH01194352 A JP H01194352A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- light
- graded
- layers
- receiving element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 16
- 150000001875 compounds Chemical class 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 230000031700 light absorption Effects 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 238000013459 approach Methods 0.000 claims description 2
- 230000007423 decrease Effects 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 6
- 238000010521 absorption reaction Methods 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 230000003287 optical effect Effects 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 101
- 238000010586 diagram Methods 0.000 description 15
- 239000000969 carrier Substances 0.000 description 9
- 229910000673 Indium arsenide Inorganic materials 0.000 description 6
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 240000002329 Inga feuillei Species 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 241000009881 Aega Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 101150024840 rmpM gene Proteins 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Junction Field-Effect Transistors (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
長波長帯の光を受光して光電変換する受光素子及びその
受光素子と増幅素子とが同一基板に形成された集積化受
信器に関し、
長波長帯の入射光に対してよりＷ電流の少ない充電変換
信号を得ることを目的とし、
受光素子は半絶縁性化合物半導体基板の上方に形成され
たＩ ｎＧａＡＳによる光吸収層と、１ｎＧａＡｓと格
子整合のある材質により、該光吸収層の両側に夫々成長
された第１及び第２のグレーデッド層と、該光吸収層に
対して光入射側に位置する該第２のグレーデッド層上に
形成されたＡｅ ｌ ｎＡｓＩ！Ｉｆと、該Ａ［Ｉ ｎ
Ａｓ１ｉ！上に形成された電極とより構成し、集積化受
信器は半絶縁性化合物半導体基板上に形成されており、
第１のグレーデッド層と同一組成の第３のグレーデッド
層と、該第３のグレーデッド層上に形成されたＩ ｎＧ
ａＡｓ１ｉＷと、該ＩｎＧａＡｓ１上に形成されたＡｌ
１ＩｎＡｓ層と、該ＡｌｎＡｓ１ｌ上に形成された電極
とよりなるトランジスタが、該半絶縁性化合物半導体基
板上に前記受光素子と共に、かつ、互いに分離して形成
するよう構成する。[Detailed Description of the Invention] [Summary] Regarding an integrated receiver in which a light-receiving element that receives light in a long wavelength band and photoelectrically converts it, and the light-receiving element and an amplification element are formed on the same substrate, The aim is to obtain a charge conversion signal with a lower W current for light, and the light receiving element is made of a light absorption layer made of InGaAS formed above a semi-insulating compound semiconductor substrate and a material that has lattice matching with InGaAs. , first and second graded layers grown on both sides of the light absorption layer, and Ael formed on the second graded layer located on the light incident side with respect to the light absorption layer. nAsI! If and the A[I n
As1i! the integrated receiver is formed on a semi-insulating compound semiconductor substrate;
a third graded layer having the same composition as the first graded layer; and an InG layer formed on the third graded layer.
aAs1iW and Al formed on the InGaAs1
A transistor including an 1InAs layer and an electrode formed on the AlnAs 1l is formed on the semi-insulating compound semiconductor substrate together with the light receiving element and separated from each other.
本発明は受光素子及び集積化受信器に係り、特に長波長
帯の光を受光して光電変換する受光素子及びその受光素
子と増幅素子とが同一基板に形成された集積化受信器に
関する。The present invention relates to a light-receiving element and an integrated receiver, and more particularly to a light-receiving element that receives light in a long wavelength band and converts it into electricity, and an integrated receiver in which the light-receiving element and an amplification element are formed on the same substrate.
受光素子として従来より第７図に示す如き断面構造のｐ
ｉｎフォトダイオード（ＰＤ）が知られている。このも
のは、電極１上にｎ＋層２，１層３゜Ｐ” ｆｆ１４及
び電極５が順次に形成された構造であり、ｉｌｉ！３が
光吸収層を構成している。Conventionally, as a light receiving element, a p
In photodiodes (PD) are known. This has a structure in which an n+ layer 2, a single layer 3.degree.
Ｐ＋層４に入射された光はｉＷ３により吸収され、ここ
でキャリア（正孔と電子）を発生し、電極１．５間に光
電流を流す。従って、１層３のルさｄ＋が小なる程キャ
リア走行時間が短くなるので、高速動作が可能となる。The light incident on the P+ layer 4 is absorbed by the iW3, where carriers (holes and electrons) are generated, and a photocurrent flows between the electrodes 1.5. Therefore, the carrier traveling time becomes shorter as the radius d+ of one layer 3 becomes smaller, and high-speed operation becomes possible.
ところが、１ｆｆ１３による光の吸収は厚さｄｌが大な
る程よく、効率の点からみるとｄｌは大なる程よい。従
って、ｉｌＥ！３の厚さｄ、は効率と速度の兼ね合いか
ら成る値に制限され、しかも、ＣＲ積による速度劣化を
防ぐためにはＰ” １２４の径を小さくしなければなら
ず、その製迄が困難であることもあり、＾連化は困難で
あった。However, the absorption of light by 1ff13 is better as the thickness dl becomes larger, and from the viewpoint of efficiency, the larger dl is, the better. Therefore, ilE! The thickness d of 3 is limited to a value that balances efficiency and speed, and furthermore, in order to prevent speed deterioration due to CR product, the diameter of P" 124 must be made small, which is difficult to manufacture. For this reason, it was difficult to establish a federation.
そこで、従来より高速動作可能な受光素子として、第８
図に示す如き構造のＭＳＭ （ｍｅｔａｌ ｓｅｍ−ｉ
ＣＯｎｄｕＣｔＯｒ ｍｅｔａｌ）フォトダイオード（
ＰＤ）が知られている。このものは、半絶縁性と化ガリ
ウム（Ｓ、Ｉ−ＧａＡｓ）基板６上に光吸収層としてノ
ンドーブヒ化ガリウム（ｉ−ＧａＡｓ）１７を形成し、
更にその上にアルミニウム（Ａｎによる電極８及び９を
形成した構造である。Therefore, as a light-receiving element that can operate at higher speed than the conventional one,
MSM (metal sem-i) with the structure shown in the figure
CONduCtOr metal) Photodiode (
PD) is known. In this case, non-doped gallium arsenide (i-GaAs) 17 is formed as a light absorption layer on a semi-insulating gallium oxide (S, I-GaAs) substrate 6,
Further, electrodes 8 and 9 made of aluminum (An) are formed thereon.
このＭＳＭフォトダイオードは、入射光により発生され
るキャリアはｒ −ｃａＡｓ層７の電極８と９との間で
走行するので、信号伝送速度は１−ＧａＡＳＩ７の厚さ
ｄｌに依存せず、電極８及び９の間隔に依存する。この
ため、厚さｄｌを厚くすることができる。In this MSM photodiode, carriers generated by incident light travel between the electrodes 8 and 9 of the r-caAs layer 7, so the signal transmission speed does not depend on the thickness dl of the 1-GaASI 7, and 9 intervals. Therefore, the thickness dl can be increased.
また、ＭＳＭフォトダイオードはブレーナ型のため、電
極８．９の面積やｐｎ接合の面積を小さくできるので、
受光面も広くできると共に容量も小さくできる。以上の
ことから、ＭＳＭフォトダイオードは萌記ｐｉｎフォト
ダイオードに比し、はるかに高速で動作することができ
る。In addition, since the MSM photodiode is a Brainer type, the area of the electrode 8.9 and the area of the pn junction can be reduced.
The light-receiving surface can be made wider and the capacity can be made smaller. From the above, the MSM photodiode can operate much faster than the Moeki pin photodiode.
しかし、このＭＳＭフォトダイオードは、０．８μ鋤程
度の短波長帯の光に対しては有効であるが、光ファイバ
の減衰が最も少ないといわれる１、６μ−程度までの長
波長帯の光を受光することはできなかった。However, although this MSM photodiode is effective for light in a short wavelength band of about 0.8μ, it is effective against light in a long wavelength band of about 1.6μ, which is said to have the least attenuation in optical fibers. It was not possible to receive light.
そこで、本出願人は先に特願昭６２−２４３６２０号に
て第９図に示す如き構造の長波長用受光素子を提案した
。すなわら、半絶縁性１ｎＰ（５，１，−ＩｎＰ）Ｗ板
１１上に１−ｉｎ ＧａＯ，４７０，５３
ＡＳＭ１１２，１−１ｎｖＧａ＋ −ｖＡｓｌｆＭ１３
（ただし、０≦Ｙ≦０．４７ ）及びｉ −ＧａＡｓＦ
ｒ４１４を順次積層し、更に１−ＧａＡｓ層１４上にア
ルミニウム（Ａ４ ）電極１５及び１６を形成した受光
素子で、光吸収層にＩｎＧａＡｓを使用することで長波
長帯の光を光電変換する構成としたものである。Therefore, the present applicant previously proposed a long wavelength light receiving element having a structure as shown in FIG. 9 in Japanese Patent Application No. 62-243620. That is, 1-in GaO, 470,53 ASM112, 1-1nvGa+ -vAslfM13 is placed on the semi-insulating 1nP (5,1,-InP) W plate 11.
(However, 0≦Y≦0.47) and i-GaAsF
This is a light receiving element in which R414 is sequentially laminated and aluminum (A4) electrodes 15 and 16 are formed on the 1-GaAs layer 14, and by using InGaAs for the light absorption layer, it has a configuration that photoelectrically converts light in a long wavelength band. This is what I did.
この本出願人の受光素子によれば、そのエネルギーバン
ド図は第１０図に示す如くになり、ノンドープのＧａＡ
ｓ層１４によりショットキー障壁の高さφＢとしてＩ
ｎＧａＡｓのそれの約０．２ｅｖに比しかなり人なる０
、８ｅＶを得ることができるので、暗電流が小さくでき
るという特長がある。According to this photodetector of the present applicant, its energy band diagram is as shown in FIG.
As the height φB of the Schottky barrier due to the s layer 14, I
0, which is considerably smaller than that of nGaAs, which is approximately 0.2ev.
, 8eV can be obtained, which has the advantage of reducing dark current.
また、本出願人は先に特願昭６２−２４３６１９号にて
例えば第１１図に示す如き構造の長波長用集積化受信器
を提案した。同図中、第９図と同一構成部分には同一符
号を付し、その説明を省略する。Furthermore, the present applicant previously proposed in Japanese Patent Application No. 62-243619 an integrated receiver for long wavelengths having a structure as shown in FIG. 11, for example. In the figure, the same components as those in FIG. 9 are denoted by the same reference numerals, and the explanation thereof will be omitted.
第１１図に示す集積化受信器は、第９図に示した構造の
ＭＳＭ−ＰＤＩ ７と同一の３．１−１ｎＰ基板１１上
方の１−ＧａＡＳｌｉｉ１４上に、更にｎ−ＧａＡＳ層
１８層形８し、その上に電極１９゜２０及び２１を形成
することにより、電界効果トランジスタ（ＦＥＴ）２２
を構成したものである。The integrated receiver shown in FIG. 11 is constructed on a 1-GaASlii 14 above a 3.1-1 nP substrate 11, which is the same as the MSM-PDI 7 having the structure shown in FIG. By forming electrodes 19, 20 and 21 thereon, a field effect transistor (FET) 22 is formed.
It is composed of
このＦＥＴ２２はＭＳＭ−ＰＤｌ７により長波長光を光
電変換して得られた電気信号を増幅して出力するための
ものである。This FET 22 is for amplifying and outputting an electrical signal obtained by photoelectrically converting long wavelength light by the MSM-PDl7.
この集積化受信器によれば、ＦＥＴ２２の大部分の層構
造がＭＳＭ−ＰＤｌ７のぞれと同じなので、製造が容易
であり、またＦＥＴ２２にＧａＡｓを用いているので高
速である等の特長がある。According to this integrated receiver, most of the layer structure of the FET 22 is the same as each of MSM-PDl7, so it is easy to manufacture, and since GaAs is used for the FET 22, it is fast. .
しかるに、上記の第９図、第１１図に夫々示した本出願
人の提案になる受光素子及び集積化受信器によれば、光
吸収層として用いられているＩｎＧａＡｓ層１２．１３
上にｒ−ＧａＡｓｍ１４を設けているが、両者は格子不
整合であるため、ＭＳＭ−ＰＤｌ ７における＠電流の
低減効果が不十分であるという問題点があった。また、
上記の本出願人の提案では、ｉ −ＧａＡｓ層１４の代
りにｉ −ＡＪ！ｘ Ｇａ＋ −ｘ Ａｓ層を設けたも
のも開示しているが、これも同様にＩｎＧａＡｓ層と格
子不整合の関係にあった。However, according to the light receiving element and integrated receiver proposed by the present applicant shown in FIGS. 9 and 11, respectively, the InGaAs layers 12 and 13 used as the light absorption layer
Although r-GaAsm 14 is provided on top, there is a problem that the current reduction effect in MSM-PDl 7 is insufficient because the two are lattice mismatched. Also,
In the above proposal of the present applicant, the i-AJ! A device in which an x Ga+ −x As layer is provided is also disclosed, but this also has a lattice mismatch relationship with the InGaAs layer.
本発明は上記の点に鑑みてなされたもので、長波長帯の
入射光に対してより暗電流の少ない光電変換信号を得る
ことができる受光素子及び集積化受信器を提供すること
を目的とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a light receiving element and an integrated receiver that can obtain a photoelectric conversion signal with less dark current for incident light in a long wavelength band. do.
（問題点を解決するための手段） 第１Ａ図は本発明になる受光素子の原理構造図を示す。(Means for solving problems) FIG. 1A shows a principle structural diagram of a light receiving element according to the present invention.
同図中、２５は半絶縁性化合物半導体基板、２６は第１
のグレーデッド層、２７は光吸収層、２８は第２のグレ
ーデッド層、２９はＡｌ１ｎＡｓ層、３０は電極である
。In the figure, 25 is a semi-insulating compound semiconductor substrate, 26 is a first
27 is a light absorption layer, 28 is a second graded layer, 29 is an Al1nAs layer, and 30 is an electrode.
光吸収層２７はＩｎＧａＡｓよりなり、その両側に第１
のグレーデッド層２６と第２のグレーデッド層２８とが
形成されている。電極３０はＡＩ！、ＩｎＡｓ１ｍ２９
上に形成されている。The light absorption layer 27 is made of InGaAs and has first layers on both sides thereof.
A graded layer 26 and a second graded layer 28 are formed. Electrode 30 is AI! , InAs1m29
formed on top.
また、第１Ｂ図は本発明になる集積化量４ｎ器の原理構
造図を示す。同図中、第１Ａ図と同一構成部分には同一
符号を付し、その説明を省略する。Further, FIG. 1B shows a principle structural diagram of a 4n device with an integrated amount according to the present invention. In the figure, the same components as in FIG. 1A are denoted by the same reference numerals, and the explanation thereof will be omitted.
第１Ｂ図において、３１は第３のグレーデッド層、３２
はＩｎＧａＡｓ層、３３はＡ［Ｉ ｎＡｓ層、３Ｃ３５
及び３６は夫々電極であり、これらはトランジスタを構
成し、前記受光素子と同一の半絶縁性化合物半導体基板
２５上に、受光素子と分離して形成されている。In FIG. 1B, 31 is the third graded layer, 32
is an InGaAs layer, 33 is an A[InAs layer, 3C35
and 36 are electrodes, which constitute a transistor and are formed separately from the light receiving element on the same semi-insulating compound semiconductor substrate 25 as the light receiving element.
なお、少なくとも第２のグレーデッド層２８はＡｌＧａ
Ｉ ｎＡｓ中のＡｔの組成の割合が光吸収層２７方向
に近付くにつれて漸次小となり、かつ、Ｇａの組成の割
合が漸次大となるようにされた、多段階の組成変化構造
である。Note that at least the second graded layer 28 is made of AlGa
This is a multi-step composition change structure in which the composition ratio of At in InAs gradually decreases as it approaches the direction of the light absorption layer 27, and the composition ratio of Ga gradually increases.
（作用）
受光素子の光吸収層２７は長波長帯材料であるるＩ ｎ
ＧａＡｓが用いられる。しかし、この１ｎＧａＡｓはシ
ョットキー障壁の高さφＢが約０．２ｅｖと低く暗電流
が問題となるので、ショットキー障壁の高さφＢを高く
し、かつ、Ｉ ｎＧａＡｓと格子整合性を確保するため
にφＢが約０．６ｅ Ｖ〜０．８ｅｖ程度のＡｔ１ ｎ
Ａｓによる層を光吸収層（ＩｎＧａＡｓ）２７上に形成
する。(Function) The light absorption layer 27 of the light receiving element is made of a long wavelength band material.
GaAs is used. However, this 1nGaAs has a low Schottky barrier height φB of about 0.2ev, which poses a problem of dark current, so in order to increase the Schottky barrier height φB and ensure lattice matching with InGaAs, At1 n with φB of about 0.6e V to 0.8ev
A layer of As is formed on the light absorption layer (InGaAs) 27.
ただし、ＩｎＧａＡｓ光吸収層上に直接ＡｆｌＩｎＡｓ
層を設けた場合は、第１２図のエネルギーバンド図に示
すように、２つの層の電子親和りの差から伝導帯の底の
ポテンシャルＥＣと価電子帯の頂上のポテンシャルＥｖ
に夫々ポテンシャルの不連続へＥＣ，へＥＶが夫々生ず
るので、■フォトキャリア（光励起キャリア）のパイル
・アップ効果のため、速度劣化を生じ、かつ、■２次元
キャリアがＡｌ１ＩｎＡｓ層と１ｎＧａＡｓ光吸収層と
の界面で生じる。However, AflInAs is directly applied to the InGaAs light absorption layer.
When layers are provided, the potential EC at the bottom of the conduction band and the potential Ev at the top of the valence band are determined from the difference in electron affinity between the two layers, as shown in the energy band diagram in Figure 12.
Since EC and EV occur due to potential discontinuity, respectively, ■ speed deterioration occurs due to the pile-up effect of photocarriers (photo-excited carriers), and ■ two-dimensional carriers are transferred to the Al1InAs layer and the 1nGaAs light absorption layer. occurs at the interface with
すなわち、第１２図に示すように、フォトキャリアは小
エネルギーのものがΔＥＣ，ΔＥＶにより走行が遮ぎら
れるので、速度劣化を生じ、また界面にキャリアの一部
が蓄憤される。That is, as shown in FIG. 12, photocarriers with low energy are blocked from traveling by ΔEC and ΔEV, resulting in speed deterioration and a portion of the carriers being accumulated at the interface.
上記の■の現象は受光素子では入射光が無くてもキャリ
アの走行をもたらし、暗電流の増加という問題を生じさ
せてしまう。The phenomenon (2) above causes carriers to travel even in the absence of incident light in the light-receiving element, resulting in the problem of increased dark current.
そこで、本発明になる受光素子は前記本出願人の問題点
を解決すると共に、上記■及び■の問題も除去するため
に、光吸収１！２７の両側に光吸収１１２７と格子整合
のある材質で第１及び第２のグレーデッド！２６及び２
８を設けたものである。Therefore, in order to solve the problem of the present applicant and also eliminate the above-mentioned problems 1 and 2, the light-receiving element of the present invention is made of a material that has lattice matching with the light absorption 1127 on both sides of the light absorption 1!27. 1st and 2nd graded! 26 and 2
8.
第２のグレーデッド層２８によりＥＣ，ＥＶが光吸収層
２７よりＡｌ１１ ｎＡｓｇ！２９にかけて漸次変化す
るので、光吸収層２７とＡ乏１ｎＡｓ層２９との界面の
八ＥＣ，ΔＥＶは実効的に無視される。また、第１及び
第２のグレーデッド層２６及び２８により、２次元キャ
リアが光吸収層２６の基板２５側との界面に形成される
現象を実質上無くすことができる。The second graded layer 28 allows EC and EV to be changed from the light absorption layer 27 to Al11 nAsg! 29, the 8EC and ΔEV at the interface between the light absorption layer 27 and the A-poor 1nAs layer 29 are effectively ignored. Moreover, the first and second graded layers 26 and 28 can substantially eliminate the phenomenon in which two-dimensional carriers are formed at the interface between the light absorption layer 26 and the substrate 25 side.
また、本発明の集積化受信器は本発明になる受光素子と
同様の構造のトランジスタを、受光素子と組み合わせて
集積化したものであり、受光素子とトランジスタとの秦
子表面間の段差は極めて小にできる。In addition, the integrated receiver of the present invention is an integrated device in which a transistor having the same structure as the light-receiving element of the present invention is combined with the light-receiving element, and the level difference between the front surfaces of the light-receiving element and the transistor is extremely small. Can be made small.
（実施例）
第２図は本発明になる受光素子の一実施例の構造断面図
を示す。同図中、４０は半絶縁細化合物半導体基板２５
の一例としてのＳ、ｌ−１ｎＰ基板、４１はＡｌ１ｎＡ
ＳＩ！、４２は八ｅＧａ ［ｎＡＳの組成変化によるグ
レーデッド層、４３は光吸収層２７に相当するＩｎＧａ
ＡｓＷＪ、４４は第２のグレーデッド層２８に相当する
グレーデッド層で、グレーデッド１ｉ４２と同一構造と
されている。更に、４５はＡｌ１ＩｎＡ５ｌ！６２９に
相当するＡｌ１ｎＡｓｌｉ、４６及び４７は夫々電極で
ある。(Embodiment) FIG. 2 shows a structural sectional view of an embodiment of the light receiving element according to the present invention. In the figure, 40 is a semi-insulating thin compound semiconductor substrate 25.
S as an example, l-1nP substrate, 41 is Al1nA
SI! , 42 is a graded layer due to a composition change of 8eGa [nAS, and 43 is an InGa layer corresponding to the light absorption layer 27.
AsWJ, 44 is a graded layer corresponding to the second graded layer 28, and has the same structure as graded 1i42. Furthermore, 45 is Al1InA5l! Al1nAsli corresponding to 629, 46 and 47 are electrodes, respectively.
Ａｌ１Ｉ ｎＡｓ層４１とグレーデッド層４２により前
記第１のグレーデッド１！２６が構成されている。The Al1I nAs layer 41 and the graded layer 42 constitute the first graded 1!26.
Ｓ、ｌ−１ｎＰＩ板４０上に分子線エピタキシャル成長
（Ｍ ３ Ｅ ： ａ＋ｏｌｅｃｕｌａｒ ｂｅａａｉ
Ｈｉｔａｘｉａｌｇｒｏｗｔｈ）法により、バッファ
の役目のＡｌｎＡＳ層４１を約４１１μｍの護りに成長
させた侵、その上にＡｌＧａ Ｉ ｎＡｓの組成比が深
さ方向に漸次異なる第１のグレーデッド層４２を例えば
２０００人の厚さに形成する。なお、Ａｔ Ｉ ｎＡＳ
層４１の代りに、ＩｎＰｌｉＷを用いてもよい。Molecular beam epitaxial growth (M 3 E: a+olecular beam epitaxial growth
An AlnAS layer 41 serving as a buffer is grown to a thickness of about 411 μm using a layer growth method (hitaxial growth), and a first graded layer 42 with a composition ratio of AlGaInAs that gradually changes in the depth direction is grown on it by, for example, 2000 people. Form to a thickness of . In addition, At I nAS
InPliW may be used instead of layer 41.
次にグレーデッド層４２上にＩｎＧａＡｓＪｉ？ｉ４３
を形成する。このｌ ｎＧａＡｓ層４３の膜厚は効率を
上げるため、例えば１．５μ量と厚くする（吸収係数は
約ｌＸ１０’１：ＩＩ−’）。Next, InGaAsJ? on the graded layer 42? i43
form. The thickness of this lnGaAs layer 43 is set to be as thick as, for example, 1.5μ in order to increase efficiency (absorption coefficient is about lX10'1:II-').
次に、ＭＢＥ法によりグレーデッドＦＷ４２と同一構造
のグレーデッドｆｆ４４を２０００人の膜厚で成長させ
た後、Ａｅ Ｉ ｎＡｓＦｇｆ４５を７００人のｇｌ厚
で形成する。以上の各層４１〜４５はすべてアンドープ
等によって低キャリアｌａ度（〜１０ Ｉ５ａｍ−３以
下）とされている。Next, a graded FF 44 having the same structure as the graded FW 42 is grown to a thickness of 2000 nm using the MBE method, and then Ae I nAsFgf 45 is formed to a GL thickness of 700 nm. All of the above layers 41 to 45 are made to have a low carrier la degree (~10 I5am-3 or less) by undoping or the like.
最後にＡｌ電極４６及び４７を夫々Ａｔ１ｎＡｓ層４５
上に３０００人の厚さで蒸着する。このＡｌ電極４６及
び４７は第３図の平面図に示す如く、櫛歯状の電極部を
有し、かつ、それらが互い違いになるように配置されて
いる。第３図に示す電極部の良さＬは一例として１００
μｍ、電極の幅之と電極間隔Ｓは夫々２μ■である。光
遮蔽を防ぐためには乏を小（例えば０，５μｍ）、Ｓを
大（例えば２μｓ）とすればよい。なお、第３図中、■
−■線に沿う断面図が第２図である。Finally, the Al electrodes 46 and 47 are connected to the At1nAs layer 45, respectively.
Deposit 3,000 layers on top. As shown in the plan view of FIG. 3, the Al electrodes 46 and 47 have comb-shaped electrode portions, and are arranged so as to alternate. The quality L of the electrode part shown in Fig. 3 is 100 as an example.
The electrode width and electrode spacing S are each 2 μm. In order to prevent light shielding, the shortness may be set small (for example, 0.5 μm) and S may be set large (for example, 2 μs). In addition, in Figure 3, ■
FIG. 2 is a sectional view taken along line -■.
次に本発明実施例の要部をなすグレーデッド層４２及び
４４について更に耳組に説明する。グレーデッドＸ１４
４は第２図及び第４図（Ｂ）に示す如＜ＡｅｌｎＡｓｌ
ｉ４５とｌ ｎＧａ八Ｓへ；！Ｎ３との間に形成されて
いるが、エネルギーギャップＥＱ （＝Ｅｃ−Ｅｖ）は
第４図（ＡＲＭ示す如くＡ［Ｉ ｎＡｓ１４５で大きく
、ｌ ｎＧａＡｓｆｆ４３で小となっている。Next, the graded layers 42 and 44, which form the main part of the embodiment of the present invention, will be further explained. Graded X14
4 is <AelnAsl> as shown in FIG. 2 and FIG. 4(B).
i45 and lnGa8S;! However, as shown in FIG. 4 (ARM), the energy gap EQ (=Ec-Ev) is large in A[InAs145 and small in InGaAsff43.
そこで、グレーデッド層４４はｌ ｎＧａＡｓと格子整
合性のあるＡｅＧａ Ｉ ｎＡＳを用い、かつ、その中
のＡｅの組成比がＡｅ Ｉ ｎＡｓＦｔｉ４５からＩ
ｎＧａＡｓｍ４３方向へ進むにつれて小となり、かつ、
Ｇａの組成比が順次大となるように段階的に変化せしめ
られ、エネルギーギャップＥｇを第４図（Ａ）に示す如
く段階的に変化させる。この段階の数は、各段階におけ
るΔＥＣ（＞△ＥＶ）が０．１ｅＶ以下となるようにす
るため、７段階以上とされている。なお、グレーデッド
層４２゜４４は実際には夫々Ａ４ Ｉ ｎＡｓ／Ｇａ
Ｉ ｎＡｓ超格子層である。Therefore, the graded layer 44 is made of AeGa I nAS which has lattice matching with I nGaAs, and the composition ratio of Ae therein is changed from Ae I nAsFti45 to I nAsFti45.
It becomes smaller as it advances toward the nGaAsm43 direction, and
The composition ratio of Ga is changed stepwise so that it becomes larger, and the energy gap Eg is changed stepwise as shown in FIG. 4(A). The number of stages is set to 7 or more so that ΔEC (>ΔEV) at each stage is 0.1 eV or less. Note that the graded layers 42 and 44 are actually A4 InAs/Ga
This is an InAs superlattice layer.
上記のＡｌ１Ｇａ Ｉ ｎＡＳ中のＡ４及びＧａの組成
の割合を変化させるには、ＭＢＥ装置のＡｅ。In order to change the composition ratio of A4 and Ga in the above-mentioned Al1GaI nAS, Ae of the MBE apparatus.
Ｇａ、Ｉｎ、Ａｓが別々に入っている各るつぼの前面に
配置された機械的シャッタの開閉の割合を夫々適宜可変
することなどにより可能である。This can be achieved by appropriately varying the opening/closing ratio of mechanical shutters placed in front of each crucible containing Ga, In, and As separately.
上記のグレーデッドＦＪ４４により、本実施例の要部の
エネルギーバンド図は第５図に示す如くになる。第５図
かられかるように、グレーデッド層４４におけるエネル
ギーギャップＥａはＡｌ２ＩｎＡｓ層４５からＩｎＧａ
Ａｓ層４３に至るにつれて漸次小となり、実質的にΔＥ
Ｖ、八ＥＣへ無視できるようになる。By using the graded FJ44 described above, the energy band diagram of the main part of this embodiment is as shown in FIG. As can be seen from FIG. 5, the energy gap Ea in the graded layer 44 is from the Al2InAs layer 45 to the InGa layer.
It gradually becomes smaller as it reaches the As layer 43, and substantially ΔE
V, becomes able to ignore 8 EC.
従って、ＩｎＧａＡｓ層４３に発生したフオｉ・キャリ
アは速度劣化が殆ど生ぜす、ＡｌＩｎＡＳ層４５との界
面に２次元キアリアが殆ど形成されないようにすること
ができる。しかも、グレーデッド層４４及び４２はｌ
ｎＧａＡｓとの格子整合がとれていることとも相まって
、本実施例によれば、暗電流が極めて少ないフオトダイ
オードを（７ることができる。Therefore, the pho-i carriers generated in the InGaAs layer 43 can be prevented from forming two-dimensional chiaria at the interface with the AlInAS layer 45, which causes almost no velocity deterioration. Moreover, the graded layers 44 and 42 are
Coupled with the fact that lattice matching with nGaAs is achieved, this embodiment makes it possible to create a photodiode with extremely low dark current.
一例として、本出願人の試作実験結束によれば、Ａ４ｍ
極線幅１μｍ、間隔１．５μｍ 、受光′？ｒＪｂＡｌ
０μＩ角のフォトダイオードにおいて、印加電圧５■で
暗電流は数ｎＡが得られ、また容Ｍは６５ｆＦが得られ
、更に波長１．３μｍの入射光に対して数十ＧＨｚの高
周波数まで平坦な充電流特性が得られた。As an example, according to the applicant's prototype experimental binding, A4m
Pole width 1μm, interval 1.5μm, light reception'? rJbAl
In a 0 μI square photodiode, an applied voltage of 5 μm results in a dark current of several nA, a capacitance M of 65 fF, and a flat rate up to a high frequency of several tens of GHz for incident light with a wavelength of 1.3 μm. Charge current characteristics were obtained.
次に本発明になる集積化受信器の一実施例について第６
図と共に説明する。同図中、第２図と同一構成部分には
同一符号を付し、その説明は省略する。Next, a sixth embodiment of the integrated receiver according to the present invention will be described.
This will be explained with figures. In the figure, the same components as those in FIG. 2 are denoted by the same reference numerals, and the explanation thereof will be omitted.
第６図中、４８及び５０は夫々Ａ［ＩｎＡｓ層、４９は
グレーデッド層、５１は前記第１Ｂ図のＡｅｌｎＡｓ層
３３に相当するＡｅ Ｉ ｎＡｓ層、５２及び５４は夫
々前記電極３４及び３６に相当するオーミック電極、５
３は前記電極３５に相当するショットキー電極である。In FIG. 6, 48 and 50 are A[InAs layers, 49 is a graded layer, 51 is an Ae I nAs layer corresponding to the AelnAs layer 33 in FIG. 1B, and 52 and 54 are A[InAs layers, respectively. Corresponding ohmic electrode, 5
3 is a Schottky electrode corresponding to the electrode 35 described above.
Ａｌ１ ｎＡｓ層４８とグレーデッドＷＪ４９が前記第
３のグレーデッド層３１に相当する。また、オーミック
電極５２及び５４は例えばＡＵＧｅＮｉからなり、ショ
ットキー電極５３は例えばＡｅからなる。The Al1 nAs layer 48 and the graded WJ 49 correspond to the third graded layer 31. Further, the ohmic electrodes 52 and 54 are made of, for example, AUGeNi, and the Schottky electrode 53 is made of, for example, Ae.
上記の集積化受信器は、まず、Ｓ、ｌ−１ｎＰ基板４０
上全面に亘って第２図に示した構成のフォトダイオード
（受光素子）を前記した方法で形成した後（ただし、こ
のとぎはまだ電極４６及び４７は形成されていない）、
トランジスタを形成すべき領域のフォトダイオード部分
を基板４０を残してエツチング除去する。The above integrated receiver first consists of an S, l-1nP substrate 40
After forming a photodiode (light receiving element) having the configuration shown in FIG. 2 over the entire upper surface by the method described above (however, electrodes 46 and 47 have not been formed yet),
The photodiode portion in the region where the transistor is to be formed is removed by etching, leaving the substrate 40 intact.
次にフォトダイオードとなるべき残った部分にＳ！３Ｎ
４１１１などを保護膜として被覆形成した後、 ・
基板４０上にＭＢＥによりフォトダイオードと同様構造
となるようＡｅＩｎＡｓ層４８、グレーデッド層４９、
ｌ ｎＧａＡｓ層５０を順次エピタキシャル成長する。Next, apply S to the remaining part that should become the photodiode! 3N
After coating with 4111 etc. as a protective film,
On the substrate 40, an AeInAs layer 48, a graded layer 49,
1 nGaAs layers 50 are epitaxially grown in sequence.
次に、ＭＢＥでＩｎＧａＡｓ１ｉ５０上にＡｌＩｎＡＳ
層５１を１００人の膜厚でエピタキシャル成長する。Ａ
乏ＩｎＡＳ層５１はシリコン（Ｓ ｉ ）などのｎ形ド
ーパントが１ ｘ １０１８ａｎ’ ｆｆ１度の濃度に
ドーピングされる。Next, AlInAS was deposited on InGaAs1i50 using MBE.
Layer 51 is epitaxially grown to a thickness of 100 nm. A
The InAS-poor layer 51 is doped with an n-type dopant such as silicon (S i ) to a concentration of 1×10 18 an' ff1 degree.
最後に、前記フォトダイオード上の保護膜を除去した後
、電極４６．４７．５３を蓄積形成し、また電極５２．
５４を周知の合金化法で形成する。Finally, after removing the protective film on the photodiode, electrodes 46, 47, 53 are deposited and electrodes 52.
54 is formed by a well-known alloying method.
上記の各層４８〜５１と電極５２〜５４はＡｌ１ｎＡｓ
層５１とＩ ｎＧａＡｓ１５０とのへテロ接合界面に形
成される２次元電子ガス（２ＤＥＧ）層をチャネル層に
使用する高電子移動度トランジスタ（１−Ｉ Ｅ Ｍ
Ｔ ）であり、電極５２，５３．５４は夫々ドレイン、
ゲート、ソースの各電極として使用される。The above layers 48 to 51 and electrodes 52 to 54 are made of Al1nAs.
A high electron mobility transistor (1-IE M
T), and the electrodes 52, 53, and 54 are the drain and the electrodes, respectively.
Used as gate and source electrodes.
このように、Ｓ、ｌ−１ｎＰ基板４０上に集積化された
ＭＳＭ−ＰＤとｌ−（ＥＭＴよりなる集積化受信器は、
ＭＳＭ−ＰＤに入射された長波長帯の光を光電変換した
後、ＨＥＭＴにより増幅して出力するよう動作し、信号
伝送速度数Ｇｂ／ｓ以上で超高速動作する。In this way, the integrated receiver consisting of the MSM-PD and l-(EMT) integrated on the S, l-1nP substrate 40 is
After photoelectrically converting the long wavelength band light incident on the MSM-PD, the HEMT operates to amplify and output the light, and operates at extremely high speed at a signal transmission rate of several Gb/s or more.
本実施例の１！１化受信器は、素子はブレーナ型で、か
つ、画素子表面間の段差は極めて小さい（約３０００人
）ので、配線パターニングされるレジストの膜厚を薄く
することができ、よってこのレジス１−をマスクどして
形成される電極４６．４７゜５２〜５４の幅を夫々細く
でき、また製作が容易である。In the 1!1 receiver of this embodiment, the element is of the Brainer type, and the level difference between the surfaces of the pixel elements is extremely small (approximately 3,000 layers), so the thickness of the resist film used for wiring patterning can be made thinner. Therefore, the widths of the electrodes 46.47.degree. 52 to 54 formed by using the resist 1- as a mask can be made thinner, and manufacturing is easy.
なお、本発明は上記の実施例に限定されるものではなく
、その他種々の変形例を包含するものである。例えば、
第１のグレーデッド層２６としてはＩ ｎＧａＡＳＰの
組成を変化させたグレーデッド構造としてもよく、また
集積化受信器中のトランジスタはＨＥＭＴ以外の構造の
ＦＥＴでもよい。Note that the present invention is not limited to the above embodiments, but includes various other modifications. for example,
The first graded layer 26 may be a graded structure in which the composition of InGaASP is changed, and the transistor in the integrated receiver may be an FET having a structure other than a HEMT.
また、受光素子や集積化受信器の製造に際しては有機金
１ＫｃＶＤ （ＭＯＣＶＤ ： ｍｅｔａｌ ｏｒｇａ
ｎｉｃｃｈｅｌｃａｌ ｖａｐｏｒ ｄｅｐｏｓｉｔｉ
ｏｎ ）法を適用することもできる。In addition, when manufacturing photodetectors and integrated receivers, organic gold 1KcVD (MOCVD) is used.
nickel vapor depositi
on ) method can also be applied.
上述の如く、本発明によれば、長波長帯材料を用、いた
光吸収層の両側に光吸収層と格子整合性のある材質で第
１及び第２のグレーデッド層を形成するようにしたので
、暗電流が極めて小さい（１μＡ以下）良好な特性を得
ることができ、またΔＥＶ、ΔＥｃの影響が実質上無視
できるので光励起キャリアのトラップが防止されて超高
速応答（１０ＧＨｚ以上）特性を得ることができ、更に
低容量で、受光領域を大にすることが可能であり、また
更に集積化受信器は受光素子部と増幅素子部との表面の
段差が極めて小さく製作が容易で、電極幅も小にするこ
とができる等の特長を有するものである。As described above, according to the present invention, the first and second graded layers are formed on both sides of the light absorption layer using a long wavelength band material and made of a material that has lattice matching with the light absorption layer. Therefore, it is possible to obtain good characteristics with an extremely small dark current (1 μA or less), and the effects of ΔEV and ΔEc are virtually negligible, preventing trapping of photoexcited carriers and obtaining ultra-high-speed response characteristics (10 GHz or more). Furthermore, the integrated receiver has a very small surface step difference between the light receiving element part and the amplifying element part, and is easy to manufacture, and the electrode width can be increased. It also has the advantage of being able to be made smaller.
第１Ａ図は本発明受光素子の原理構造図、第１Ｂ図は本
発明集積化受信器の原理＃Ｉ構造図第２図は本発明受光
素子の一実施例の構造断面図、
第３図は第２図中の電極の一例の平面図、第４図は第２
図の要部の構成説明図、
第５図は本発明の一実施例のエネルギーバンド図、
第６図は本発明の集積化受信器の一実施例の構造断面図
、
第７図はｐ１ｎフォトダイオードの一例の断面構造図、
第８図はＭＳＭフォｌ〜ダイオードの一例の構造断面図
、
第９図は本出願人が先に提案した受光系子の一例の構造
断面図、
第１０図は第９図のエネルギーバンド図、第１１図は本
出願人が先に提案した集積化受信器の一例の構造断面図
、
第１２図はｌ ｎＧａＡｓ層上にＡｆｌｌｎＡｓ層を設
けた場合の受光素子のエネルギーバンド図である。
図において、
２５は半絶縁性化合物半導体基板、
２６は第１のグレーデッド層、
２７はＩ ｎＧａＡｓ光吸収層、
２８は第２のグレーデッド層
２９．３３はＡ［Ｉ ｎＡｓＬ？ｆ
３０．３４〜３Ｇは電極、
３１は第３のグレーデッド層、
３２は１ｎＧａΔｓ１５．
４０は半絶縁性ｒｎｐＭ板、
４２．４４．４９はＡＪ！Ｇａ１ｎＡｓによるグレーデ
ッド層
を示す。
本発明受光素子の原理構造図
第１Ａ図
本発明集積化受信器の原理構造図
第１８図
本発明受光素子の一実施例の構造断面図第２図
第２図の要部の構成説明図
本発明の一実施例のエネルプーバンド図第５図
本発明の集積化受信器の一実施例の構造断面図第６図
第７図 第８図
ΔＩ
本出願人が先に提案した受光素子の
一例の構造断面図
第９図
第９図のエネルイーバンド図
第１０図Fig. 1A is a structural diagram of the principle of the light receiving element of the present invention, Fig. 1B is a structural diagram of principle #I of the integrated receiver of the present invention, Fig. 2 is a structural sectional view of an embodiment of the light receiving element of the present invention, and Fig. 3 is A plan view of an example of the electrode in Fig. 2, Fig. 4 is a plan view of an example of the electrode in Fig. 2;
Figure 5 is an energy band diagram of an embodiment of the present invention; Figure 6 is a cross-sectional view of the structure of an embodiment of the integrated receiver of the present invention; Figure 7 is a p1n photo Figure 8 is a cross-sectional view of an example of a diode, Figure 8 is a cross-sectional view of an example of a MSM diode, Figure 9 is a cross-sectional view of an example of a light-receiving element previously proposed by the applicant, and Figure 10 is FIG. 9 is an energy band diagram, FIG. 11 is a cross-sectional view of the structure of an example of an integrated receiver previously proposed by the applicant, and FIG. 12 is a photodetector element when an AfllnAs layer is provided on the lnGaAs layer. It is an energy band diagram. In the figure, 25 is a semi-insulating compound semiconductor substrate, 26 is a first graded layer, 27 is an InGaAs light absorption layer, 28 is a second graded layer 29.33 is A[InAsL? f 30.34-3G are electrodes, 31 is the third graded layer, 32 is 1nGaΔs15. 40 is a semi-insulating rmpM board, 42.44.49 is AJ! A graded layer of Ga1nAs is shown. Figure 1A is a diagram of the principle structure of the light receiving element of the present invention. Figure 18 is a diagram of the principle structure of the integrated receiver of the present invention. Figure 2 is a structural sectional view of an embodiment of the light receiving element of the present invention. Energy band diagram of an embodiment of the invention FIG. 5 Structural sectional view of an embodiment of the integrated receiver of the invention FIG. 6 FIG. 7 FIG. 8 ΔI An example of a light-receiving element previously proposed by the applicant Fig. 9 Structural cross-sectional diagram of Fig. 9 Energy-E band diagram of Fig. 9 Fig. 10
Claims (3)
されたＩｎＧａＡｓによる光吸収層（２７）と、 ＩｎＧａＡｓと格子整合のある材質により、該光吸収層
（２７）の両側に夫々成長された第１及び第２のグレー
デッド層（２６、２８）と、該光吸収層（２７）に対し
て光入射側に位置する該第２のグレーデッド層（２８）
上に形成されたＡｌＩｎＡｓ層（２９）と、 該ＡｌＩｎＡｓ層（２９）上に形成された電極（３０）
とよりなることを特徴とする受光素子。(1) A light absorption layer (27) made of InGaAs formed above the semi-insulating compound semiconductor substrate (25), and a light absorption layer (27) made of a material lattice matched to InGaAs grown on both sides of the light absorption layer (27). first and second graded layers (26, 28), and the second graded layer (28) located on the light incident side with respect to the light absorption layer (27).
an AlInAs layer (29) formed above, and an electrode (30) formed on the AlInAs layer (29)
A light receiving element characterized by:
ＡｌＧａＩｎＡｓ中のＡｌ及びＧａのうちＡｌの組成の
割合が該光吸収層（２７）方向に近付くにつれて漸次小
となり、かつ、Ｇａの組成の割合が漸次大となる、多段
階の組成変化構造であることを特徴とする請求項１記載
の受光素子。(2) At least the second graded layer (28)
It has a multi-step compositional change structure in which the composition ratio of Al among Al and Ga in AlGaInAs gradually decreases as it approaches the light absorption layer (27) direction, and the composition ratio of Ga gradually increases. The light receiving element according to claim 1, characterized in that:
ており、前記第１のグレーデッド層（２６）と同一組成
の第３のグレーデッド層（３１）と、該第３のグレーデ
ッド層（３１）上に形成されたＩｎＧａＡｓ層（３２）
と、 該ＩｎＧａＡｓ層（３２）上に形成された ＡｅＩｎＡｓ層（３３）と、 該ＡｌＩｎＡｓ層（３３）上に形成された電極（３４、
３５、３６）とよりなるトランジスタが、該半絶縁性化
合物半導体基板（２５）上に請求項１記載の受光素子と
共に、かつ、互いに分離して形成されてなることを特徴
とする集積化受信器。(3) a third graded layer (31) formed on the semi-insulating compound semiconductor substrate (25) and having the same composition as the first graded layer (26); InGaAs layer (32) formed on layer (31)
an AeInAs layer (33) formed on the InGaAs layer (32); and an electrode (34) formed on the AlInAs layer (33).
35, 36) are formed on the semi-insulating compound semiconductor substrate (25) together with the light receiving element according to claim 1 and separated from each other. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63018391A JPH01194352A (en) | 1988-01-28 | 1988-01-28 | Photo detector and integrated receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63018391A JPH01194352A (en) | 1988-01-28 | 1988-01-28 | Photo detector and integrated receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01194352A true JPH01194352A (en) | 1989-08-04 |
Family
ID=11970411
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63018391A Pending JPH01194352A (en) | 1988-01-28 | 1988-01-28 | Photo detector and integrated receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01194352A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5107318A (en) * | 1990-04-16 | 1992-04-21 | Fujitsu Limited | Semiconductor device having light receiving diode element with capacitance |
| US5185272A (en) * | 1990-04-16 | 1993-02-09 | Fujitsu Limited | Method of producing semiconductor device having light receiving element with capacitance |
| JP2006229156A (en) * | 2005-02-21 | 2006-08-31 | Ntt Electornics Corp | Photodiode |
| WO2008026536A1 (en) * | 2006-08-29 | 2008-03-06 | Hamamatsu Photonics K.K. | Photodetector and method for manufacturing photodetector |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5320881A (en) * | 1976-08-11 | 1978-02-25 | Nippon Telegr & Teleph Corp <Ntt> | Photo semiconductor device |
| JPS5984417A (en) * | 1982-11-04 | 1984-05-16 | Nec Corp | Iii-v family mixed crystalline semiconductor device |
| JPS61276314A (en) * | 1985-05-31 | 1986-12-06 | Fujitsu Ltd | Liquid-phase epitaxial growth method of compound semiconductor |
| JPS62159477A (en) * | 1986-01-08 | 1987-07-15 | Fujitsu Ltd | Photosemiconductor device |
-
1988
- 1988-01-28 JP JP63018391A patent/JPH01194352A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5320881A (en) * | 1976-08-11 | 1978-02-25 | Nippon Telegr & Teleph Corp <Ntt> | Photo semiconductor device |
| JPS5984417A (en) * | 1982-11-04 | 1984-05-16 | Nec Corp | Iii-v family mixed crystalline semiconductor device |
| JPS61276314A (en) * | 1985-05-31 | 1986-12-06 | Fujitsu Ltd | Liquid-phase epitaxial growth method of compound semiconductor |
| JPS62159477A (en) * | 1986-01-08 | 1987-07-15 | Fujitsu Ltd | Photosemiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5107318A (en) * | 1990-04-16 | 1992-04-21 | Fujitsu Limited | Semiconductor device having light receiving diode element with capacitance |
| US5185272A (en) * | 1990-04-16 | 1993-02-09 | Fujitsu Limited | Method of producing semiconductor device having light receiving element with capacitance |
| JP2006229156A (en) * | 2005-02-21 | 2006-08-31 | Ntt Electornics Corp | Photodiode |
| WO2008026536A1 (en) * | 2006-08-29 | 2008-03-06 | Hamamatsu Photonics K.K. | Photodetector and method for manufacturing photodetector |
| JP2008060161A (en) * | 2006-08-29 | 2008-03-13 | Hamamatsu Photonics Kk | Optical detector, and method of manufacturing optical detector |
| US8101940B2 (en) | 2006-08-29 | 2012-01-24 | Hamamatsu Photonics K.K. | Photodetector and method for manufacturing photodetector |
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