JPS5961054A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5961054A
JPS5961054A JP57169515A JP16951582A JPS5961054A JP S5961054 A JPS5961054 A JP S5961054A JP 57169515 A JP57169515 A JP 57169515A JP 16951582 A JP16951582 A JP 16951582A JP S5961054 A JPS5961054 A JP S5961054A
Authority
JP
Japan
Prior art keywords
layer
alumina
lead
semiconductor device
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57169515A
Other languages
Japanese (ja)
Other versions
JPS638621B2 (en
Inventor
Masahiro Sugimoto
杉本　正浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57169515A priority Critical patent/JPS5961054A/en
Publication of JPS5961054A publication Critical patent/JPS5961054A/en
Publication of JPS638621B2 publication Critical patent/JPS638621B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

PURPOSE:To stabilize the insulation property by enhancing the adhesion strength of a lead pin by a method wherein a conductor pattern is formed on an Si carbide substrate whereon an alumina layer has been formed, and then the lead pin is brazed to the pattern. CONSTITUTION:An SiO2 film 6 is formed on the surface of the Si carbide substrate 1, and the alumina paste layer 10 is baked on the film 6. For the purpose of a pad, an Mo/Mn paste layer 11 is coated over the surface of the layer 10 and baked. The external lead pin 5 is brazed to the layer 11 by means of Au solder. Thereby, the installation of the pad and the pin can be performed at a high temperature, and therefore the adhesion strength improves.

Description

【発明の詳細な説明】 （１）発明の技術分野 本発明は炭化珪素基板に端子のリードビンをアルミナペ
ーストを介在して接着せしめた半導体装置に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device in which lead bins of terminals are bonded to a silicon carbide substrate with an alumina paste interposed therebetween.

（２）技術の背景 半導体部品はチップの保護、配線板への搭載の必要性か
ら・ぐッケーソに封入される。この場合チップは通常チ
ップ接着のパッドと端子引出し線をメタライズしたセラ
ミック基板上に接着しリードをビンディングしてふたを
のせてシールする。セラミック基板はアルミナ（Ａｔ２
０５）が主として用いられている。しかし半導体集積回
路チップが大型化し、且つノ・イ・ぐワー化、高密度化
し消費電力が増大する傾向になるにつれて最近熱伝導率
が良く、線膨張係数がシリコンにほぼ等しく、且つセラ
ミック基板に対して強度の旨い炭化珪素（ＳｔＣ）基板
がセラミック基板の代わりに使われるようになってきて
いる。(2) Background of the technology Semiconductor parts are sealed in packaging because of the need to protect the chips and mount them on wiring boards. In this case, the chip is usually bonded with chip bonding pads and terminal lead wires on a metallized ceramic substrate, the leads are bound, and a lid is placed on the substrate for sealing. The ceramic substrate is alumina (At2
05) is mainly used. However, as semiconductor integrated circuit chips have become larger, and have become more compact and dense, resulting in increased power consumption, ceramic substrates have recently become available with good thermal conductivity, a coefficient of linear expansion almost equal to that of silicon, and ceramic substrates. On the other hand, strong silicon carbide (StC) substrates have come to be used instead of ceramic substrates.

（３）従来技術の問題点 第１図は半導体パッケージを示す概略断面図であり、第
２図は第１図のＸ、Ｙ切断面を示す。(3) Problems with the Prior Art FIG. 1 is a schematic sectional view showing a semiconductor package, and FIG. 2 is a cross-sectional view taken along the X and Y sides of FIG. 1.

第１図及び第２図においてＳｉＣ基板１にチッ７″２が
載置されており、該チップ２からＳＩＣ基板１へ配線３
が形成されており該チップ２及び配線３をシールするよ
うにキャップ４が配設されている。又ＳＩＣ基板には外
部と電気的に接続させるために（外部）リードビンがＡ
点で接着されている〇 第３図は第１図のＡ点近傍の従来構造を説明するだめの
也す１別所面図である。In FIGS. 1 and 2, a chip 7''2 is mounted on a SiC substrate 1, and a wiring 3 is connected from the chip 2 to the SIC substrate 1.
A cap 4 is provided to seal the chip 2 and the wiring 3. Also, the SIC board has an (external) lead bin A for electrical connection to the outside.
Figure 3, which is attached at points 〇, is a cross-sectional view for explaining the conventional structure in the vicinity of point A in Figure 1.

第３図において、約１５ないし３咽の厚さを有するＳＩ
Ｃ基板１に３ないし１０μｍの厚みの８１０２膜６を設
は史にその上にＳｉＣを絶縁するため市販グレーズ用の
ガラス膜７が２０〜３０μｍの厚みに設けられ、そして
該グレーズ用ガラス膜７上にＣｕのペースト８のノミタ
ーンが８００〜１０００℃で焼付けられており、前述の
外部と電気的接続を得るため外部リード５がＣｕの４−
ス）８にハンダ付け９せしめられている。このような構
造によって得られたり−ドビン５はハンダ付は強度に本
質的に左右されそのｆ＋Ｍは５　ｋ、９　／ｒａｎ２程
度であり０４５φ叫の径のピンであれば１〜２に９／本
程度でハンダ付は部又はリードビンが破壊する。史に又
グレーズ用ガラス膜７Ｃｕ−！−ストを焼付けるのに窒
素がス雰囲気中で８００〜１０００℃の温度で行なわれ
るが、この処理中にガラス膜７が還元されて絶縁性が低
下することがある。Ｃｕ　＜−ストの代わりにＰｄ／Ａ
ｇ　、　Ｐｔ／Ａｇ又はＡｕ　”！−スト等を用いて行
ガえばＣｕ　ｄ−ストを用いる場合のような窒素雰囲気
中で焼付ける必要がなくガラス膜７の絶縁性は維持され
るものの、貴金属のためコストが高くつく。また強度的
にも十分なものが得られない。In Figure 3, the SI having a thickness of about 15 to 3 throats
Historically, an 8102 film 6 with a thickness of 3 to 10 μm is provided on the C substrate 1, and a glass film 7 for commercially available glazes with a thickness of 20 to 30 μm is provided thereon to insulate the SiC. A chisel turn of Cu paste 8 is baked on top at 800 to 1000°C, and an external lead 5 is made of Cu paste 8 in order to obtain the electrical connection with the outside.
S) 8 is soldered to 9. Soldering is essentially dependent on strength, and its f+M is about 5 k, 9/ran2, and if the pin has a diameter of 045φ, it will be 9/ran2 in 1 to 2. In some cases, the soldering part or the lead bottle will be destroyed. Glass film for glaze 7Cu-! - Baking is carried out at a temperature of 800 to 1000 DEG C. in a nitrogen gas atmosphere, but during this process the glass film 7 may be reduced and its insulation properties may be reduced. Pd/A instead of Cu <-st
If this is done using a Cu, Pt/Ag or Au''!-st, it is not necessary to bake in a nitrogen atmosphere as in the case of using a Cu d-st, and the insulation properties of the glass film 7 are maintained; Therefore, the cost is high.Also, it is not possible to obtain a product with sufficient strength.

（４）発明の目的 上記欠点を鑑み本発明の目的はリードピン強度が強く且
つＳｉＣ基板に対する絶縁性の安定した信頼性のある半
導体装置を提供することである。(4) Object of the Invention In view of the above drawbacks, an object of the present invention is to provide a reliable semiconductor device with strong lead pin strength and stable insulation with respect to a SiC substrate.

（５）発明の措成 本発明の目的は表面にアルミナ層の形成された炭化珪素
基板に導体・ぐターンを形成し該導体・Ｐターンにリー
ドビンをろう刺してなることを特徴とする半導体装置に
よって達成される。(5) Accomplishment of the Invention The object of the present invention is to provide a semiconductor device characterized in that a conductor/P-turn is formed on a silicon carbide substrate having an alumina layer formed on the surface thereof, and a lead bottle is soldered to the conductor/P-turn. achieved.

すなわち本発明の半導体装置は従来のグレーズ用ｉｆラ
ス膜の代わりにアルミナペーストを用い、又・ぐラド用
金属としてＣｕ　、　Ｐｄ／Ａｇ等の代わりに高融点金
属を用い、更に端子であるリードビンをハンダ付でなく
硬ろう付けによって該・やラド金属に接合せしめた構造
である。That is, the semiconductor device of the present invention uses alumina paste instead of the conventional IF lath film for glazing, uses a high melting point metal instead of Cu, Pd/Ag, etc. as the metal for glazing, and also uses lead bins as terminals. It has a structure in which it is joined to the metal by hard brazing rather than soldering.

なお本発明では炭化珪素基板とアルミナ（Ａｔ２０３）
ベー＝　Ｌ　Ａ・ｉとの間に二酸化珪素（Ｓ　：０２　
）膜を介在さぜるのがＳｉＣ基板の絶縁性を高める上で
好ましい。Note that in the present invention, a silicon carbide substrate and alumina (At203) are used.
Silicon dioxide (S:02
) It is preferable to interpose a film in order to improve the insulation properties of the SiC substrate.

（６）発明の実施例 以下本発明を実施例に基づいて詳細に説明する。(6) Examples of the invention The present invention will be described in detail below based on examples.

第４図は本発明に係る実施例を説明するだめの概略断面
図である。FIG. 4 is a schematic sectional view for explaining an embodiment of the present invention.

第４図に示すように、炭化珪素基板１表面上に膜厚が３
ないし１０μｍのＳ　ｒ　０２　Ｎ　６が１４００ない
し１４５０℃の酸化処理によって形成されており、５Ｉ
０２膜６上にアルミナイースト層１０が公知のスクリー
ン印刷によって形成され且つ１５００ないし１６００℃
の高温で５ＩＯ２膜と密着性よく焼付けられており、且
つアルミナ被−スト層１０の表面にパッド用としてＭｏ
／Ｍｎのペースト層１１を塗布後、１４００ないし１４
５０℃で焼付けられ、更にＭｏ／Ｍｎの４−スト層１１
に外部リードビン５が銀ろう１２を用いてろう付けされ
ている。またアルミナに一ストは高融点を有するので高
融点金属のＭｏ／Ｍｎペーストの他にＭｏ　、　Ｗ等の
金属に一ストも上記のような１４００ないし１５５０℃
の高温で密着性よくアルミナ啄−スト層］Ｏに被着♂し
められる。又密着性よくアルミナペースト層１０に被着
されたＭｏ７’Ｍｎ　’−スト層に捧コパールからなる
外部リードビン５を銀ろう１２を用いて８００ないし８
３０℃で窒素と水素の混合力゛ス中で硬ろう付けされて
いる。本発明の、都合アルミナペーストを用いることに
よって従来より高温でパッド及びリードビンの取り付け
を行なうことが可能となり、従って密着強度が向上する
。銀ろう付された状態で例えば径が０．４５間のリード
ビンの引張り強度は１本当たり８ないし１０ｋｉｌｉ’
と従来の５〜１０倍程度になりリードビン相費そのもの
の強度に迄向上する。又Ｓ　ｒ　０２膜６はなくともア
ルミナペースト層１０によってＳｉＣ基板１との絶縁優
ろうの他にマンガンろう真ちゅうろうでもよい。As shown in FIG.
S r 02 N 6 of 10 μm to 10 μm is formed by oxidation treatment at 1400 to 1450° C., and 5I
An alumina yeast layer 10 is formed on the 02 membrane 6 by a known screen printing method and heated at 1500 to 1600°C.
It is baked with good adhesion to the 5IO2 film at a high temperature of
1400 to 14 after applying the paste layer 11 of /Mn
Baked at 50°C and further coated with Mo/Mn 4-st layer 11
An external lead bin 5 is soldered to the top using silver solder 12. In addition, since alumina has a high melting point, in addition to the high melting point metal Mo/Mn paste, metals such as Mo and W can also be heated at 1400 to 1550°C as mentioned above.
The alumina-strength layer is adhered to [O] with good adhesion at high temperatures. Further, an external lead bottle 5 made of copal is bonded to the Mo7'Mn'-st layer, which is adhered to the alumina paste layer 10 with good adhesion, using a silver solder 12.
It is hard-brazed in a mixed force of nitrogen and hydrogen at 30°C. By using the convenient alumina paste of the present invention, it is possible to attach pads and lead bins at higher temperatures than in the past, and therefore the adhesion strength is improved. For example, the tensile strength of a lead bottle with a diameter of 0.45 in the silver soldered state is 8 to 10 kili' per bottle.
The strength is about 5 to 10 times that of the conventional one, and the strength is improved to the level of the lead bin cost itself. Further, the S r 02 film 6 may be made of manganese solder or brass solder in addition to the alumina paste layer 10 that provides good insulation with the SiC substrate 1 .

そのようなろう付けの前に無電解ニッケルを金属部にメ
ッキしたシ、ヌリードビン５をろう付は後更に金属部に
ニッケ歩合等をメッキするのは従来技術と同様である〇 （７）発明の効果 り、上訴明したように本発明に係る半導体装置によれば
強いリードビン強度と、ＳＩＣ基板に対する安定した絶
縁性を得て、高い信頼性を得ることが出来る。The metal parts are plated with electroless nickel before such brazing, and the metal parts are further plated with nickel after brazing the Nu Lead Bin 5, as in the prior art.〇(7) According to the invention Effectively, as stated in the appeal, the semiconductor device according to the present invention can provide strong lead bin strength and stable insulation with respect to the SIC substrate, resulting in high reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第２図は半導体・ゼッケーソを説明するだめ
の概略図であり、第３図は第１図のＡ点近傍の従来構造
を説明するだめの概略断面図であり、第４図は本発明に
係る実施例を説明するための概１格断面図である。 １・・ＳｉＣ基板、２・・・半導体チップ、３・・・配
線、４・・・キャップ、５・・・リードビン、６・・・
５１０２　ＡＱ、７・・・グレーズ用ガラス膜、８・・
ｐｄ／Ａｇ−２−スト層、９・・・ハンダ、１０・・・
アルミナ梨−スト層、１１・・・ＭＯ／Ｍｎ層、１２・
・・銀ろう。 第１　図 第２図 第３図 第４図FIGS. 1 and 2 are schematic diagrams for explaining the semiconductor/Zekkeso, FIG. 3 is a schematic sectional view for explaining the conventional structure near point A in FIG. 1, and FIG. FIG. 1 is an approximately 1-case cross-sectional view for explaining an embodiment of the present invention. 1...SiC substrate, 2...semiconductor chip, 3...wiring, 4...cap, 5...lead bin, 6...
5102 AQ, 7... Glass film for glaze, 8...
pd/Ag-2-st layer, 9... solder, 10...
Alumina pear-stone layer, 11...MO/Mn layer, 12.
...Silver wax. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】 １゜表面にアルミナ層の形成された灰化珪素基板に導体
・ぞターンを形成し、該導体ｉｊターンにリードビンを
ろう付してなることを特徴とする半導体装置。 ２　前記炭化珪素基板と前記アルミナ層間に二酸化シリ
コン膜を介在せしめることを特徴とする特許請求の範囲
第１項記載の半導体装置。[Scope of Claims] A semiconductor device comprising: a silicon ash substrate having an alumina layer formed on its 1° surface; conductor zot turns formed thereon; and lead bottles brazed to the conductor ij turns. 2. The semiconductor device according to claim 1, wherein a silicon dioxide film is interposed between the silicon carbide substrate and the alumina layer.
JP57169515A 1982-09-30 1982-09-30 Semiconductor device Granted JPS5961054A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57169515A JPS5961054A (en) 1982-09-30 1982-09-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57169515A JPS5961054A (en) 1982-09-30 1982-09-30 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5961054A true JPS5961054A (en) 1984-04-07
JPS638621B2 JPS638621B2 (en) 1988-02-23

Family

ID=15887933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57169515A Granted JPS5961054A (en) 1982-09-30 1982-09-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5961054A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6054652A (en) * 1997-04-18 2000-04-25 Fujitsu Limited Thin-film multi-layer substrate and electronic device
US8096039B2 (en) 2003-08-11 2012-01-17 Cobra Golf Incorporated Golf club head with alignment system
US8308583B2 (en) 2003-08-11 2012-11-13 Cobra Golf Incorporated Golf club head with alignment system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6054652A (en) * 1997-04-18 2000-04-25 Fujitsu Limited Thin-film multi-layer substrate and electronic device
US8096039B2 (en) 2003-08-11 2012-01-17 Cobra Golf Incorporated Golf club head with alignment system
US8308583B2 (en) 2003-08-11 2012-11-13 Cobra Golf Incorporated Golf club head with alignment system

Also Published As

Publication number Publication date
JPS638621B2 (en) 1988-02-23

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