JP2813072B2 - Package for storing semiconductor elements - Google Patents
Package for storing semiconductor elementsInfo
- Publication number
- JP2813072B2 JP2813072B2 JP3068930A JP6893091A JP2813072B2 JP 2813072 B2 JP2813072 B2 JP 2813072B2 JP 3068930 A JP3068930 A JP 3068930A JP 6893091 A JP6893091 A JP 6893091A JP 2813072 B2 JP2813072 B2 JP 2813072B2
- Authority
- JP
- Japan
- Prior art keywords
- metal
- insulating base
- integrated circuit
- semiconductor integrated
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路素子を収
容するための半導体素子収納用パッケージの改良に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor device housing package for housing a semiconductor integrated circuit device.
【０００２】[0002]
【従来の技術】従来、半導体素子、特にLSI 等の半導体
集積回路素子を収容するための半導体素子収納用パッケ
ージは、一般にアルミナセラミックス等の電気絶縁材料
から成り、その上面略中央部に半導体集積回路素子を収
容するための凹部を有し、且つ上面にタングステン(W)
、モリブデン(Mo)等の高融点金属粉末から成るメタラ
イズ配線層を有する絶縁基体と、半導体集積回路素子を
外部電気回路に電気的に接続するために前記メタライズ
配線層に銀ロウ等のロウ材を介し取着された外部リード
端子と、コバール金属や42アロイ等の金属から成る金属
製蓋体とから構成されており、絶縁基体の凹部底面に半
導体集積回路素子を取着収容し、半導体集積回路素子の
各電極とメタライズ配線層とをボンディングワイヤを介
して接続するとともに絶縁基体上面に金属製蓋体を金−
錫合金（Au-Sn 合金) 等から成る封止材により接合さ
せ、絶縁基体と金属製蓋体とから成る容器の内部に半導
体集積回路素子を気密に封止することによって最終製品
としての半導体装置となる。2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element, particularly a semiconductor integrated circuit element such as an LSI, is generally made of an electrically insulating material such as alumina ceramics, and has a semiconductor integrated circuit located substantially at the center of its upper surface. Has a recess for accommodating the element, and tungsten (W) on the upper surface
An insulating base having a metallized wiring layer made of a high melting point metal powder such as molybdenum (Mo), and a brazing material such as silver braze in the metallized wiring layer for electrically connecting a semiconductor integrated circuit element to an external electric circuit. And a metal lid made of a metal such as Kovar metal or 42 alloy. The semiconductor integrated circuit element is mounted and accommodated on the bottom surface of the concave portion of the insulating base. Each electrode of the element is connected to the metallized wiring layer via a bonding wire, and a metal cover is formed on the upper surface of the insulating base by a metal.
A semiconductor device as a final product by joining with a sealing material made of a tin alloy (Au-Sn alloy) or the like, and hermetically sealing the semiconductor integrated circuit element inside a container consisting of an insulating base and a metal lid. Becomes
【０００３】しかしながら、近時、半導体集積回路素子
の大型化、信号の伝播速度の高速化が急激に進み、該半
導体集積回路素子を上記従来の半導体素子収納用パッケ
ージに収容した場合、以下に述べる欠点を有したものと
なる。In recent years, however, the size of semiconductor integrated circuit devices and the speed of signal propagation have rapidly increased, and when the semiconductor integrated circuit devices are housed in the conventional semiconductor device housing package, the following will be described. It has disadvantages.
【０００４】即ち、(1) 半導体集積回路素子を構成する
シリコンとパッケージの絶縁基体を構成するアルミナセ
ラミックスの熱膨張係数がそれぞれ3.0 〜3.5 ×10-6/
℃、6.0 〜7.5 ×10-6/ ℃であり、大きく相違すること
から両者に半導体集積回路素子を作動させた際等に発生
する熱が印加されると両者間に大きな熱応力が発生し、
該熱応力によって半導体集積回路素子が破損したり、絶
縁基体より剥離して半導体装置としての機能を喪失させ
てしまうThat is, (1) the coefficient of thermal expansion of silicon constituting a semiconductor integrated circuit element and the coefficient of thermal expansion of alumina ceramic constituting an insulating base of a package are 3.0 to 3.5 × 10 -6 /
℃, 6.0 to 7.5 × 10 -6 / ℃, greatly different from the heat generated when operating the semiconductor integrated circuit element and the like is applied to both, a large thermal stress occurs between the two,
The thermal stress damages the semiconductor integrated circuit element or peels off from the insulating base to cause the semiconductor device to lose its function as a semiconductor device.
【０００５】(2) パッケージの絶縁基体を構成するアル
ミナセラミックスはその誘電率が9 〜10( 室温1MHz) と
高いため、絶縁基体に設けたメタライズ配線層を伝わる
信号の伝播速度が遅く、そのため信号の高速伝播を要求
する半導体集積回路素子はその搭載収容が不可となる等
の欠点を有していた。(2) Since the dielectric constant of alumina ceramic constituting the insulating base of the package is as high as 9 to 10 (room temperature 1 MHz), the propagation speed of the signal transmitted through the metallized wiring layer provided on the insulating base is slow, and A semiconductor integrated circuit element that requires high-speed propagation has a drawback that it cannot be mounted and accommodated.
【０００６】そこで上記欠点を解消するために半導体素
子収納用パッケージの絶縁基体をアルミナセラミックス
に代えて半導体集積回路素子を構成するシリコンの熱膨
張係数(3.0〜3.5 ×10-6/ ℃) と近似した熱膨張係数4.
0 〜4.5 ×10-6/ ℃を有し、且つ誘電率が6.3 と低いム
ライト質焼結体を用いることが検討されている。Therefore, in order to solve the above-mentioned drawback, the thermal expansion coefficient of the silicon constituting the semiconductor integrated circuit device (3.0 to 3.5 × 10 -6 / ° C.) is approximated by replacing the insulating base of the semiconductor device housing package with alumina ceramics. Thermal expansion coefficient 4.
Use of a mullite sintered body having a temperature of 0 to 4.5 × 10 −6 / ° C. and a low dielectric constant of 6.3 has been studied.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、このム
ライト質焼結体をパッケージの絶縁基体として使用した
場合、絶縁基体に金属製蓋体を金−錫合金等の封止材を
介して接合すると絶縁基体（ムライト質焼結体）と金属
製蓋体（コバール金属や42Alloy ）の熱膨張係数がそれ
ぞれ4.0 〜4.5 ×10-6/ ℃、:5.2〜6.0 ×10-6/ ℃) と
相違することから両者の熱膨張係数の相違に起因する熱
応力が接合部に内在し、その結果、金属製蓋体に小さな
外力が印加されても該外力は前記内在応力と相俊って大
きくなり、金属製蓋体を絶縁基体より剥がれさせ、容器
の気密封止を破ってしまうという問題を有していた。However, when the mullite sintered body is used as an insulating base of a package, the metal cover is bonded to the insulating base via a sealing material such as a gold-tin alloy. The coefficient of thermal expansion of the substrate (mullite sintered body) and the metal lid (Kovar metal or 42Alloy) are different from 4.0 to 4.5 × 10 -6 / ° C, respectively: 5.2 to 6.0 × 10 -6 / ° C. From the thermal stress due to the difference in the coefficient of thermal expansion of the two is inherent in the joint, as a result, even if a small external force is applied to the metal lid, the external force increases rapidly with the intrinsic stress, metal There has been a problem that the lid-made body is peeled off from the insulating base and the hermetic sealing of the container is broken.
【０００８】[0008]
【課題を解決するための手段】本発明は半導体素子を収
容するための凹部を有する絶縁基体と金属製蓋体とから
成る半導体素子収納用パッケージにおいて、前記絶縁基
体をムライト質焼結体で形成し、且つ金属製蓋体をニッ
ケル41.5乃至42.5重量％、鉄57.5乃至58.5重量％の合金
から成る芯体の外表面に銅から成る被覆層を、該被覆層
の断面積が芯体の断面積の20乃至40% となるように被着
させた金属体で形成したことを特徴とするものである。According to the present invention, there is provided a semiconductor element housing package comprising a metal cover and an insulating base having a recess for housing a semiconductor element, wherein the insulating base is formed of a mullite sintered body. A metal cover is made of an alloy of 41.5 to 42.5% by weight of nickel and 57.5 to 58.5% by weight of iron, and a coating layer made of copper is provided on the outer surface of the core. It is characterized by being formed of a metal body adhered so as to be 20 to 40% of the above.
【０００９】[0009]
【実施例】次に本発明を添付図面に示す実施例に基づき
詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the embodiments shown in the accompanying drawings.
【００１０】図１は本発明にかかる半導体素子収納用パ
ッケージの一実施例を示す断面図であり、1 は絶縁基
体、2 は金属製蓋体である。この絶縁基体1 と金属製蓋
体2 とで半導体集積回路素子4 を収容するための容器3
が構成される。FIG. 1 is a sectional view showing one embodiment of a package for housing a semiconductor element according to the present invention, wherein 1 is an insulating base, and 2 is a metal lid. A container 3 for accommodating the semiconductor integrated circuit device 4 with the insulating base 1 and the metal lid 2.
Is configured.
【００１１】前記絶縁基体1 はその上面中央部に半導体
集積回路素子4を収容するための空所を形成する段状の
凹部Ａが設けてあり、凹部Ａ底面には半導体集積回路素
子4が接着材を介し取着される。The insulating substrate 1 is provided with a stepped recess A for forming a space for accommodating the semiconductor integrated circuit element 4 at the center of the upper surface thereof, and the semiconductor integrated circuit element 4 is adhered to the bottom of the recess A. It is attached via materials.
【００１２】前記絶縁基体1 はムライト質焼結体から成
り、該ムライト質焼結体はその熱膨張係数が4.0 〜4.5
×10-6/ ℃であり、半導体集積回路素子4 を構成するシ
リコンの熱膨張係数(3.0〜3.5 ×10-6/ ℃) と近似する
ことから絶縁基体1 の凹部Ａ底面に半導体集積回路素子
4 を取着収容した後、両者に半導体集積回路素子4 を作
動させた際等に発生する熱が印加されたとしても両者間
には大きな熱応力が発生することはなく、該熱応力によ
って半導体集積回路素子4 が破損したり、絶縁基体1 よ
り剥離したりすることはない。The insulating substrate 1 is made of a mullite sintered body, and the mullite sintered body has a thermal expansion coefficient of 4.0 to 4.5.
× 10 −6 / ° C., which is close to the coefficient of thermal expansion (3.0 to 3.5 × 10 −6 / ° C.) of the silicon constituting the semiconductor integrated circuit element 4.
Even if heat generated when the semiconductor integrated circuit element 4 is operated is applied to both of them after mounting and housing 4, no large thermal stress is generated between the two. The integrated circuit element 4 is not damaged or peeled from the insulating base 1.
【００１３】尚、前記ムライト質焼結体から成る絶縁基
体1 は例えば、ムライト（3 Al 2 O3・2SiO2 ) 、シリ
カ(SiO2 ) 、マグネシア(MgO) 、カルシア(CaO) 等の原
料粉末に適当な有機溶剤、溶媒を添加混合して泥漿状と
なすとともにこれをドクターブレード法を採用すること
によってセラミックグリーンシート( セラミック生シー
ト) を形成し、しかる後、前記セラミックグリーンシー
トに適当な打ち抜き加工を施すとともに複数枚積層し、
高温（1400〜1800℃) で焼成することによって製作され
る。[0013] The insulating substrate 1 made of the mullite sintered body, for example, mullite (3 Al 2 O 3 · 2SiO 2), silica (SiO 2), magnesia (MgO), raw material powders such as calcia (CaO) An appropriate organic solvent and a solvent are added and mixed to form a slurry, and this is formed into a ceramic green sheet (ceramic green sheet) by employing a doctor blade method. Thereafter, the ceramic green sheet is appropriately punched. Applying processing and laminating multiple sheets,
It is manufactured by firing at a high temperature (1400-1800 ° C).
【００１４】また前記絶縁基体1 には凹部Ａの周辺から
容器3 の外部にかけてメタライズ配線層5 が形成されて
おり、該メタライズ配線層5 の凹部Ａ周辺部には半導体
集積回路素子4 の各電極がボンディングワイヤ6 を介し
電気的に接続され、また容器3 の外部に導出された部位
には外部電気回路と接続される外部リード端子7 が銀ロ
ウ等のロウ材8 を介し取着されている。A metallized wiring layer 5 is formed on the insulating base 1 from the periphery of the concave portion A to the outside of the container 3, and each electrode of the semiconductor integrated circuit element 4 is formed around the concave portion A of the metallized wiring layer 5. Are electrically connected via bonding wires 6, and external lead terminals 7 connected to an external electric circuit are attached to a portion led out of the container 3 via a brazing material 8 such as silver brazing. .
【００１５】前記メタライズ金属層5 はタングステン、
モリブデン等の高融点金属粉末から成り、従来周知のス
クリーン印刷法等の厚膜手法を採用することによって絶
縁基体1 の凹部Ａ周辺から容器3 の外部に導出するよう
被着形成される。The metallized metal layer 5 is made of tungsten,
It is made of a high melting point metal powder such as molybdenum, and is formed so as to be led out of the container 3 from the periphery of the concave portion A of the insulating substrate 1 by employing a conventionally known thick film method such as a screen printing method.
【００１６】前記メタライズ配線層5 は絶縁基体1 を構
成するムライト質焼結体の誘電率が6.3 と低いことから
それを伝わる電気信号の伝播速度を極めて速いものとな
すことができ、これによってパッケージ内に信号の伝播
速度が速い高速駆動を行う半導体集積回路素子4 を収容
することも可能となる。Since the metallized wiring layer 5 has a low dielectric constant of 6.3, which is a mullite sintered body constituting the insulating substrate 1, it is possible to make the propagation speed of an electric signal transmitted through the metallized wiring layer extremely high. It is also possible to accommodate therein a semiconductor integrated circuit element 4 that performs high-speed driving with a high signal propagation speed.
【００１７】また前記メタライズ配線層5 にロウ付けさ
れる外部リード端子7 は内部に収容する半導体集積回路
素子4 を外部電気回路に接続する作用を為し、外部リー
ド端子7 を外部電気回路に接続することによって内部に
収容される半導体集積回路素子4 はメタライズ配線層5
及び外部リード端子7 を介し外部電気回路に電気的に接
続されることとなる。An external lead terminal 7 brazed to the metallized wiring layer 5 serves to connect the semiconductor integrated circuit element 4 housed therein to an external electric circuit, and connects the external lead terminal 7 to the external electric circuit. As a result, the semiconductor integrated circuit element 4 accommodated inside is
In addition, it is electrically connected to an external electric circuit via the external lead terminal 7.
【００１８】前記外部リード端子7 はコバール金属や42
Alloy 等の金属から成り、コバール金属等のインゴット
( 塊) を従来周知の圧延加工法を採用することによって
所定の板状に形成される。The external lead terminal 7 is made of Kovar metal or 42
Ingots made of metals such as Alloy and Kovar metals
(Lump) is formed into a predetermined plate shape by employing a conventionally known rolling method.
【００１９】また前記絶縁基体1 にはその上面にメタラ
イズ金属層9 が被着形成されており、該メタライズ金属
層9 上には金属製蓋体2 が金−錫合金等の封止材10を介
し接合されている。On the upper surface of the insulating substrate 1, a metallized metal layer 9 is adhered. On the metallized metal layer 9, a metal cover 2 is provided with a sealing material 10 such as a gold-tin alloy. Are joined through.
【００２０】前記絶縁基体1 上面のメタライズ金属層9
はタングステン、モリブデン等の高融点金属粉末から成
り、該タングステン粉末等に適当な有機溶剤、溶媒を添
加混合して得た金属ペーストを絶縁基体1 の上面に従来
周知のスクリーン印刷法により印刷塗布するとともにこ
れを高温で焼き付けることによって絶縁基体1 の上面に
被着形成される。The metallized metal layer 9 on the upper surface of the insulating substrate 1
Is made of a high melting point metal powder such as tungsten or molybdenum, and a metal paste obtained by adding and mixing an appropriate organic solvent and a solvent to the tungsten powder or the like is printed and applied on the upper surface of the insulating substrate 1 by a conventionally known screen printing method. At the same time, by baking this at a high temperature, it is formed on the upper surface of the insulating substrate 1.
【００２１】また前記メタライズ金属層9 に接合される
金属製蓋体2 はニッケル41.5乃至42.5重量％、鉄57.5乃
至58.5重量％の合金から成る芯体の外表面に銅から成る
被覆層を、該被覆層の断面積が芯体の断面積の20乃至40
% となるように被着させた金属体から成り、その熱膨張
係数が4.7 〜4.9 ×10-6/℃のものとなっている。The metal cover 2 bonded to the metallized metal layer 9 has a core made of an alloy of 41.5 to 42.5% by weight of nickel and 57.5 to 58.5% by weight of iron, and has a coating layer made of copper on the outer surface. The cross-sectional area of the coating layer is 20 to 40 of the cross-sectional area of the core body.
%, And has a coefficient of thermal expansion of 4.7 to 4.9 × 10 −6 / ° C.
【００２２】前記金属製蓋体2 はその熱膨張係数が4.7
〜4.9 ×10-6/ ℃であり、絶縁基体1 を構成するムライ
ト質焼結体の熱膨張係数と近似していることから絶縁基
体1に被着させたメタライズ金属層9 に金属製蓋体2 を
封止材を介して接合する際、絶縁基体1 と金属製蓋体2
との間には両者の熱膨張係数の相違に起因する大きな熱
応力が発生することはなく、両者の接合部に大きな応力
が内在することもない。従って、接合後、金属製蓋体2
に外力が印加されたとしても該外力が接合部に内在する
応力と相俊って大となり、金属製蓋体2 を絶縁基体1 よ
り剥がれさせることはない。The metal lid 2 has a thermal expansion coefficient of 4.7.
4.9 × 10 −6 / ° C., which is close to the coefficient of thermal expansion of the mullite sintered body composing the insulating substrate 1, so that the metalized metal layer 9 applied to the insulating substrate 1 2 are bonded via the sealing material, the insulating base 1 and the metal lid 2
No large thermal stress due to the difference in the coefficient of thermal expansion between the two occurs, and no large stress is inherent in the joint between the two. Therefore, after joining, the metal lid 2
Even if an external force is applied to the metal cover, the external force becomes large rapidly with the stress existing in the joint, and the metal cover 2 does not peel off from the insulating base 1.
【００２３】尚、前記金属製蓋体2 は、例えばニッケル
41.5乃至42.5重量％、鉄57.5乃至58.5重量％を加熱溶融
させてニッケルー鉄合金のインゴット( 塊) を作り、次
に前記インゴットの外表面に銅を圧接させ、しかる後、
これを圧延することによって製作される。The metal cover 2 is made of, for example, nickel.
41.5 to 42.5% by weight and 57.5 to 58.5% by weight of iron are heated and melted to form an ingot of a nickel-iron alloy, and then copper is pressed against the outer surface of the ingot.
It is manufactured by rolling this.
【００２４】また前記金属製蓋体2 はニッケル、鉄の量
及び芯体と被覆層の断面積の比率が上述した範囲から外
れると金属枠体10の熱膨張係数が絶縁基体1 を構成する
ムライト質焼結体に対して大きくなりすぎ、その結果、
金属製蓋体2 を絶縁基体1 に強固に取着させることがで
きなくなる。従って、前記金属製蓋体2 はニッケル41.5
乃至42.5重量％、鉄57.5乃至58.5重量％の合金から成る
芯体の外表面に銅から成る被覆層を、該被覆層の断面積
が芯体の断面積の20乃至40%となるように被着させた金
属体で形成するものに特定される。When the amount of nickel and iron and the ratio of the cross-sectional area of the core to the covering layer are out of the above-mentioned ranges, the coefficient of thermal expansion of the metal frame 10 becomes the mullite that forms the insulating base 1. Is too large for the high quality sintered body,
The metal lid 2 cannot be firmly attached to the insulating base 1. Therefore, the metal lid 2 is made of nickel 41.5
To a core layer composed of an alloy containing 57.5 to 58.5% by weight of iron, and a coating layer made of copper on the outer surface of the core so that the cross-sectional area of the coating layer is 20 to 40% of the cross-sectional area of the core body. It is specified to be formed of a metal body that has been attached.
【００２５】また前記メタライズ金属層9 及び金属製蓋
体2 はその各々の露出外表面にニッケル、金等の耐蝕性
に優れた金属をメッキにより2.0 乃至20.0μm の厚みに
層着させておくとメタライズ金属層9 及び金属製蓋体2
が酸化腐食し、変色するのを有効に防止することができ
る。従って、メタライズ金属層9 及び金属製蓋体2 の露
出外表面には酸化腐食による変色を有効に防止するため
にニッケル、金等を2.0 乃至20.0μm の厚みに層着して
おくことが好ましい。The metallized metal layer 9 and the metal lid 2 may be formed by plating a metal having excellent corrosion resistance, such as nickel or gold, to a thickness of 2.0 to 20.0 μm on the exposed outer surfaces thereof by plating. Metallized metal layer 9 and metal lid 2
Can be effectively prevented from oxidative corrosion and discoloration. Therefore, it is preferable to coat nickel, gold or the like on the exposed outer surfaces of the metallized metal layer 9 and the metal lid 2 to a thickness of 2.0 to 20.0 μm in order to effectively prevent discoloration due to oxidative corrosion.
【００２６】かくして本発明の半導体素子収納用パッケ
ージによれば絶縁基体1 の凹部A 底面に半導体集積回路
素子4 を接着材を介し取着するとともに半導体集積回路
素子4 の各電極をメタライズ配線層5 にボンディングワ
イヤ6 を介し電気的に接続し、しかる後、絶縁基体1 の
上面に金属製蓋体2 を金−錫合金等の封止材を介して接
合し、容器3 の内部を気密に封止することによって製品
としての半導体装置となる。Thus, according to the package for accommodating a semiconductor device of the present invention, the semiconductor integrated circuit device 4 is attached to the bottom surface of the concave portion A of the insulating base 1 via an adhesive, and each electrode of the semiconductor integrated circuit device 4 is connected to the metallized wiring layer 5. Then, a metal lid 2 is bonded to the upper surface of the insulating base 1 via a sealing material such as a gold-tin alloy, and the inside of the container 3 is hermetically sealed. By stopping, a semiconductor device as a product is obtained.
【００２７】尚、本発明は上述した実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能であり、例えば外部リード端子7 を金
属製蓋体2 と同じ金属体、即ち、ニッケル41.5乃至42.5
重量％、鉄57.5乃至58.5重量％の合金から成る芯体の外
表面に銅から成る被覆層を、該被覆層の断面積が芯体の
断面積の20乃至40% となるように被着させた金属体を使
用すれば外部リード端子7 の絶縁基体1 への取着が極め
て強固なものとなる。従って、外部リード端子7 を絶縁
基体1 に極めて強固に取着させるには外部リード端子7
をニッケル41.5乃至42.5重量％、鉄57.5乃至58.5重量％
の合金から成る芯体の外表面に銅から成る被覆層を、該
被覆層の断面積が芯体の断面積の20乃至40% となるよう
に被着させた金属体で形成しておくことが好ましい。It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. For example, the external lead terminal 7 can be connected to the metal cover 2. Metal body, i.e., nickel 41.5-42.5
A core layer made of an alloy containing 57.5 to 58.5% by weight of iron and a coating layer made of copper is applied to the outer surface of the core such that the cross-sectional area of the coating layer is 20 to 40% of the cross-sectional area of the core body. If the metal body is used, the attachment of the external lead terminals 7 to the insulating base 1 becomes extremely strong. Therefore, in order to attach the external lead terminal 7 very firmly to the insulating substrate 1, the external lead terminal 7
The nickel 41.5-42.5% by weight, iron 57.5-58.5% by weight
A coating layer made of copper is formed on the outer surface of a core body made of an alloy of the above, with a metal body adhered so that the cross-sectional area of the coating layer is 20 to 40% of the cross-sectional area of the core body. Is preferred.
【００２８】また外部リード端子7 の露出外表面にニッ
ケル、金等の耐蝕性に優れ、且つ良導電性である金属を
メッキにより2.0 乃至20.0μm の厚みに層着させておく
と外部リード端子7 が酸化腐食し、変色するのを有効に
防止することができるとともに外部リード端子7 と外部
電気回路との電気的接続を極めて良好なものとなすこと
ができる。従って、外部リード端子7 の酸化腐食による
変色を有効に防止し、且つ外部電気回路との電気的接続
を良好とするためには外部リード端子7 の露出外表面に
ニッケル、金等を2.0 乃至20.0μm の厚みに層着してお
くことが好ましい。Further, a metal having excellent corrosion resistance and good conductivity, such as nickel or gold, may be plated on the exposed outer surface of the external lead terminal 7 to a thickness of 2.0 to 20.0 μm by plating. Can be effectively prevented from being oxidized and corroded and discolored, and the electrical connection between the external lead terminal 7 and the external electric circuit can be made extremely good. Accordingly, in order to effectively prevent discoloration of the external lead terminal 7 due to oxidative corrosion and to improve the electrical connection with an external electric circuit, nickel, gold or the like is coated on the exposed external surface of the external lead terminal 7 with 2.0 to 20.0%. It is preferable to coat the layer to a thickness of μm.
【００２９】[0029]
【発明の効果】本発明の半導体素子収納用パッケージに
よれば、絶縁基体をムライト質焼結体で形成したことか
ら絶縁基体の熱膨張係数を半導体集積回路素子の熱膨張
係数に近似させることができ、その結果、絶縁基体の凹
部内に半導体集積回路素子を収容した後、半導体集積回
路素子を作動させた際等に発生する熱が絶縁基体と半導
体集積回路素子の両者に印加されたとしても両者間には
大きな熱応力が発生することはなく、該熱応力によって
半導体集積回路素子が破損したり、絶縁基体より剥離し
たりすることはない。According to the package for accommodating a semiconductor element of the present invention, since the insulating base is formed of a mullite sintered body, the thermal expansion coefficient of the insulating base can be approximated to the thermal expansion coefficient of the semiconductor integrated circuit element. As a result, even when the semiconductor integrated circuit element is housed in the concave portion of the insulating base and heat generated when the semiconductor integrated circuit element is operated is applied to both the insulating base and the semiconductor integrated circuit element. No large thermal stress is generated between the two, and the thermal stress does not damage the semiconductor integrated circuit element or peel off from the insulating base.
【００３０】またムライト質焼結体より成る絶縁基体は
その誘電率が6.3 と低いため該絶縁基体に設けたメタラ
イズ配線層を伝わる電気信号の伝播速度を極めて速いも
のとなすことができ、その結果、パッケージの容器内部
に高速駆動を行う半導体集積回路素子の収容も可能とな
る。Further, since the insulating base made of a mullite sintered body has a low dielectric constant of 6.3, the propagation speed of an electric signal transmitted through the metallized wiring layer provided on the insulating base can be made extremely high. In addition, a semiconductor integrated circuit element that operates at high speed can be accommodated in the package container.
【００３１】更に金属製蓋体をニッケル41.5乃至42.5重
量％、鉄57.5乃至58.5重量％の合金から成る芯体の外表
面に銅から成る被覆層を、該被覆層の断面積が芯体の断
面積の20乃至40% となるように被着させた金属体で形成
したことからその熱膨張係数を絶縁基体に近似させるこ
とができ、その結果、絶縁基体の上面に金属製蓋体を接
合させる際、絶縁基体と金属製蓋体との間には両者の熱
膨張係数の相違に起因する熱応力は殆ど発生せず、絶縁
基体上面に金属製蓋体を極めて強固に接合させることを
可能として高信頼性の半導体素子収納用パッケージを提
供することもできる。Further, the metal lid is made of an alloy of 41.5 to 42.5% by weight of nickel and 57.5 to 58.5% by weight of iron, and a coating layer made of copper is provided on the outer surface of the core. The thermal expansion coefficient can be approximated to that of the insulating base because it is formed of a metal body applied so as to have an area of 20 to 40%, and as a result, the metal lid is joined to the upper surface of the insulating base. At this time, almost no thermal stress is generated between the insulating base and the metal lid due to the difference in thermal expansion coefficient between the two, and the metal lid can be bonded extremely firmly to the upper surface of the insulating base. A highly reliable semiconductor element housing package can also be provided.
【図１】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.
１・・・絶縁基体 ２・・・金属製蓋体 ３・・・容器 ５・・・メタライズ配線層 ７・・・外部リード端子 ９・・・メタライズ金属層 １０・・封止材 Ａ・・・凹部 DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Metal lid 3 ... Container 5 ... Metallized wiring layer 7 ... External lead terminal 9 ... Metallized metal layer 10 ... Sealing material A ... Recess
Claims (1)
絶縁基体と金属製蓋体とから成る半導体素子収納用パッ
ケージにおいて、前記絶縁基体をムライト質焼結体で形
成し、且つ金属製蓋体をニッケル41.5乃至42.5重量％、
鉄57.5乃至58.5重量％の合金から成る芯体の外表面に銅
から成る被覆層を、該被覆層の断面積が芯体の断面積の
20乃至40% となるように被着させた金属体で形成したこ
とを特徴とする半導体素子収納用パッケージ。1. A semiconductor element housing package comprising an insulating base having a concave portion for housing a semiconductor element and a metal lid, wherein the insulating base is formed of a mullite sintered body, and the metal lid is provided. The nickel 41.5-42.5% by weight,
A coating layer made of copper is provided on the outer surface of a core made of an alloy containing 57.5 to 58.5% by weight of iron, and the cross-sectional area of the coating layer is smaller than that of the core.
A package for housing a semiconductor element, which is formed of a metal body adhered so as to have a concentration of 20 to 40%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3068930A JP2813072B2 (en) | 1991-03-08 | 1991-03-08 | Package for storing semiconductor elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3068930A JP2813072B2 (en) | 1991-03-08 | 1991-03-08 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04280653A JPH04280653A (en) | 1992-10-06 |
| JP2813072B2 true JP2813072B2 (en) | 1998-10-22 |
Family
ID=13387872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3068930A Expired - Fee Related JP2813072B2 (en) | 1991-03-08 | 1991-03-08 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2813072B2 (en) |
-
1991
- 1991-03-08 JP JP3068930A patent/JP2813072B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04280653A (en) | 1992-10-06 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |