JPS5959035U

JPS5959035U - A-D converter

Info

Publication number: JPS5959035U
Application number: JP15331982U
Authority: JP
Inventors: 村上　芳廣; 誠新納; 畠　尚平
Original assignee: ソニー株式会社
Priority date: 1982-10-09
Filing date: 1982-10-09
Publication date: 1984-04-17

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の直並列型Ａ−Ｄ変換装置の一例の接続図
、第２図はその第１段及び第２段のＡ−Ｄ変換器の一例
の接続図、第３図は本考案のＡ−−−Ｄ変換装置の一実
施例を示す接続図、第４図はその要部の基準電圧発生回
路の具体例の接続図、第５図は基準電圧発生回路の別の
例の接続図、第６図〜第８図は第３図の実施例の動作の
説明のための図である。図中、１０は入力端子、２０は第１段のＡ−Ｄ変換器、
０１〜Ｃ１５は電圧比較器、２３はエンコーダー１９０
は基準電圧発生回路、５０は遅延回路、７０は第２段の
Ａ−Ｄ変換器、８０はデジタル合成器である。第７図第８図Fig. 1 is a connection diagram of an example of a conventional serial-parallel type A-D converter, Fig. 2 is a connection diagram of an example of the first and second stage A-D converters, and Fig. 3 is a connection diagram of the present invention. 4 is a connection diagram showing a specific example of the reference voltage generation circuit, which is the main part of the A--D converter, and FIG. 5 is a connection diagram of another example of the reference voltage generation circuit. 6 to 8 are diagrams for explaining the operation of the embodiment shown in FIG. 3. In the figure, 10 is an input terminal, 20 is a first stage A-D converter,
01 to C15 are voltage comparators, 23 is an encoder 190
50 is a reference voltage generation circuit, 50 is a delay circuit, 70 is a second-stage AD converter, and 80 is a digital synthesizer. Figure 7 Figure 8

Claims

【実用新案登録請求の範囲】[Scope of utility model registration request]

アナログ入力電圧を夫々一定電位ずつ順次異なる基準電
圧と比較する複数の電圧比較器及びこの複数の電圧比較
器の出力を符号化して上記アナログ入力電圧をＡ、−Ｄ
変換した所要ビット数の２進符号信号を得るエンコーダ
ーを有する第１段のＡ−り変換器と、この第１段のＡ−
、−Ｄ変換器の上記複数の電圧比較器の出力から−、各
電圧比較器の出力を上記アナログ入力電圧がその電圧比
較器の基準電圧量子であるか基準電圧に満たないかに応
じて１またはＯて表わしたときの、上記複数の電圧比較
器の出力の総和をＸとするとき、電圧Ｖ）、１＝ＸＶ□
＋Ｖ２及びＶＬ＝Ｖ、４−Ｖ３（ただし、ｖ、、　ｖ２
及びＶ３は一定電圧）を発生させる基準電圧発生回路と
、この゛　　　　基準電圧発生回路から得られる上記電
圧■８及び′■、を夫々動作範囲の上限及び下限の基準
電圧として上記アナログ入力電圧をＡ−Ｄ変換して所要
ビット数の２進符号信号を得る第２段のＡ−Ｄ変換器と
、上記第１段及び第２段のＡ−Ｄ変換器の出力の２進符
号信号を合成して所定ビット数の２連符号信号を得るデ
ジタル合成器とからなるＡ−Ｄ変換装置。A plurality of voltage comparators sequentially compare the analog input voltage with different reference voltages by a constant potential, and the outputs of the plurality of voltage comparators are encoded to convert the analog input voltage to A, -D.
a first-stage A-reconverter having an encoder for obtaining a converted binary code signal of the required number of bits;
, - from the outputs of the plurality of voltage comparators of the D converter - the output of each voltage comparator is set to 1 or 1 depending on whether the analog input voltage is the reference voltage quantum of that voltage comparator or less than the reference voltage. When the sum of the outputs of the plurality of voltage comparators is expressed as O, voltage V), 1=XV□
+V2 and VL=V, 4-V3 (where v,, v2
and V3 are constant voltages), and the analog input voltage is set to A, using the voltages ``8'' and ``■'' obtained from this standard voltage generating circuit as reference voltages at the upper and lower limits of the operating range, respectively. - A second stage A-D converter which performs D conversion to obtain a binary code signal with the required number of bits, and combines the binary code signals output from the first and second stage A-D converters. and a digital synthesizer for obtaining a double code signal of a predetermined number of bits.