JPH01200672A - Coplanar transistor and manufacture thereof - Google Patents
Coplanar transistor and manufacture thereofInfo
- Publication number
- JPH01200672A JPH01200672A JP2368688A JP2368688A JPH01200672A JP H01200672 A JPH01200672 A JP H01200672A JP 2368688 A JP2368688 A JP 2368688A JP 2368688 A JP2368688 A JP 2368688A JP H01200672 A JPH01200672 A JP H01200672A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- gate
- insulating film
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000010408 film Substances 0.000 claims abstract description 87
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000010409 thin film Substances 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 239000011229 interlayer Substances 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- 238000000206 photolithography Methods 0.000 claims description 6
- 239000011159 matrix material Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- 239000005360 phosphosilicate glass Substances 0.000 claims 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 239000007789 gas Substances 0.000 abstract description 7
- 239000002994 raw material Substances 0.000 abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 abstract description 2
- 239000011261 inert gas Substances 0.000 abstract description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 2
- 238000011109 contamination Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多結晶シリコンとゲート絶縁膜界面の形成を清
浄化プロセスで行なう薄膜トランジスタに係り、連続形
成とセルファライン方式の単純化プロセスによる薄膜ト
ランジスタに関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a thin film transistor in which the interface between polycrystalline silicon and a gate insulating film is formed by a cleaning process, and relates to a thin film transistor using a simplified process of continuous formation and self-line method. .
従来の薄膜トランジスタは例えば特開昭５８−３２４５
１に記載され、その内容は第２図に示すとおりである。Conventional thin film transistors are disclosed in Japanese Patent Application Laid-Open No. 58-3245, for example.
1, and its contents are as shown in Figure 2.
（１）のＣＶＤ酸化膜１をデポした絶縁基板２上に多結
晶シリコン３を形成し、続いてＣＶＤシリコン酸化膜４
をかぶせホトリソグラフィーによってレジストパターン
５を形成し、ＣＶＤシリコン酸化膜４をエッチカットす
る。さらにこのＣＶＤシリコン酸化膜４パターンをマス
クに（２）、のように多結晶シリコン３の島カットの後
、除去する。このＣＶＤシリコン酸化ｖ４は多結晶シリ
コン３表面の汚れを防止するためである。このエツチン
グによって（３）のよう多結晶シリコン３下のＣＶＤ酸
化膜１も上部のＣＶＤシリコン酸化膜４と同程度の膜厚
がエツチングされ段差部を生ずる欠点がある。次に（４
）のようにゲート絶縁膜６．多結晶シリコン７の順に膜
形成する。A polycrystalline silicon 3 is formed on the insulating substrate 2 on which the CVD oxide film 1 of (1) has been deposited, and then a CVD silicon oxide film 4 is formed.
A resist pattern 5 is formed by photolithography, and the CVD silicon oxide film 4 is etched and cut. Furthermore, using this CVD silicon oxide film 4 pattern as a mask, islands of polycrystalline silicon 3 are cut and removed as shown in (2). This CVD silicon oxidation v4 is to prevent the surface of the polycrystalline silicon 3 from becoming contaminated. As a result of this etching, the CVD oxide film 1 under the polycrystalline silicon 3 is etched to a thickness comparable to that of the CVD silicon oxide film 4 above, resulting in a step portion. Next (4
), the gate insulating film 6. Films of polycrystalline silicon 7 are formed in this order.
次に（５）に示したが、所定領域以外の多結晶シリコン
７をホトリソグラフィーによってエツチングし、さらに
多結晶シリコン７をマスクに下層のゲート絶縁膜６のエ
ツチングをする。続いて基板全体に熱拡散をほどこしソ
ース８およびドレイン９部にｐ÷拡散層を形成する０次
に（６）の如くＣＶＤ酸化膜１０を基板全体に堆積した
後コンタクトホールを開孔する。次にＡＱ−２％Ｓｉを
スパッタリングしホトエツチングし配線加工を施してい
る。Next, as shown in (5), the polycrystalline silicon 7 other than the predetermined area is etched by photolithography, and the underlying gate insulating film 6 is etched using the polycrystalline silicon 7 as a mask. Subsequently, thermal diffusion is applied to the entire substrate to form a p/diffusion layer in the source 8 and drain 9 portions.After depositing a CVD oxide film 10 over the entire substrate as shown in (6), a contact hole is formed. Next, wiring was processed by sputtering AQ-2% Si and photoetching.
上記従来技術は第２図（１）、（２）に示したように、
多結晶シリコン３の島状加工に当って。As shown in FIG. 2 (1) and (2), the above conventional technology
When processing polycrystalline silicon 3 into an island shape.
マスクとしてのレジスタ５が多結晶シリコン３表面を汚
染しないよう表面カバー用にＣＶＤシリコン酸化膜４を
かぶせること。また多結晶シリコン３のパターニング後
に該ＣＶＤシリコン酸化膜をエツチング除去しなければ
ならない面倒な方法が採用されている。A CVD silicon oxide film 4 is covered as a surface cover so that the resistor 5 as a mask does not contaminate the surface of the polycrystalline silicon 3. Furthermore, a cumbersome method is used in which the CVD silicon oxide film must be removed by etching after patterning the polycrystalline silicon 3.
本発明の目的は製造プロセスが短く、界面が清浄化され
るコプレーナ薄膜トランジスタを考案することにある。An object of the present invention is to devise a coplanar thin film transistor with a short manufacturing process and a clean interface.
上記目的は薄膜トランジスタを製作するに当り、透明絶
縁基板上に多結晶シリコン膜、ゲート絶縁膜、低抵抗多
結晶シリコン膜を連続して成膜することにより、多結晶
シリコンとゲート絶縁膜の界面の汚れをなくしている。The above purpose is to form thin film transistors by successively forming a polycrystalline silicon film, a gate insulating film, and a low-resistance polycrystalline silicon film on a transparent insulating substrate. Eliminates dirt.
なおソース・ドレイン部の形成に当っては、ホトリソグ
ラフィーによってチャネル部を形成するゲート絶縁膜と
上層の低抵抗多結晶シリコン膜をほぼ同形状にマスクし
、所要領域以外の低抵抗多結晶シリコン膜、ゲート絶縁
膜をエツチング除去した後、イオン打込みでセルファラ
インの接合形成ができる。この後イオン打込み層を活性
化し、基板全面を層間絶縁膜で被覆した後、コンタクト
形成をし電極蒸着をして。When forming the source/drain parts, the gate insulating film forming the channel part and the upper low-resistance polycrystalline silicon film are masked in almost the same shape by photolithography, and the low-resistance polycrystalline silicon film is removed in areas other than the required areas. After removing the gate insulating film by etching, a self-line junction can be formed by ion implantation. After this, the ion implantation layer is activated, the entire surface of the substrate is covered with an interlayer insulating film, contacts are formed, and electrodes are deposited.
ゲート・ソース・ドレイン電極を基板面上に引き出しア
クティブマトリクスのデータ線とゲート線に接続するこ
とによって達成される。This is achieved by extending the gate, source, and drain electrodes onto the substrate surface and connecting them to the data lines and gate lines of the active matrix.
〔作用〕
薄膜トランジスタを製作するに当り、多結晶シリコン上
にゲート絶縁膜を連続成膜しており、レジスト介在等に
おける界面汚染が解消される。また、ゲート層も連続形
成して、セルファライン方法で接合形成し１層間絶縁膜
によってゲート・ソ−ス・ドレインの基板面上への配線
の引き出しを可能とした簡易プロセスであり、良好な素
子特性が得られる。[Function] When manufacturing a thin film transistor, a gate insulating film is continuously formed on polycrystalline silicon, and interface contamination caused by intervening resist or the like is eliminated. In addition, it is a simple process in which the gate layer is also formed continuously, and the junction is formed using the self-line method, and the gate, source, and drain wiring can be drawn out onto the substrate surface using a single interlayer insulating film, resulting in a good device. characteristics are obtained.
以下本発明の詳細な説明する。第１図は本発明による薄
膜トランジスタの製作プロセス図である。まず（１）−
に示したように絶縁基板２上に多結晶シリコン膜３．ゲ
ート絶縁暎６．リンドープした低抵抗ゲート多結晶シリ
コン膜１１を連続成膜する。膜形成は多結晶シリコン膜
３はモノシランガスを原料に、減圧ＣＶＤ法により５８
０℃で成膜した。膜厚は１０００人である。ゲート絶縁
膜６は常圧ＣＶＤ法により容積で不活性キャリアガス９
０％に対し原料ガス（モノシランガス：酸素＝４ ：
３）を１０％の流量比で流し、温度４８０℃のもとで膜
厚１０００人を形成した。ゲート多結晶シリコン膜１１
は番号３の多結晶シリコン膜と同じ条件で膜厚を１００
０人形成した後、基板全体にリンの熱拡散をほどこし膜
を低抵抗化した。The present invention will be explained in detail below. FIG. 1 is a process diagram for manufacturing a thin film transistor according to the present invention. First (1)-
As shown in , a polycrystalline silicon film 3. is formed on an insulating substrate 2. Gate insulation 6. A phosphorus-doped low resistance gate polycrystalline silicon film 11 is successively formed. The polycrystalline silicon film 3 is formed using monosilane gas as a raw material by low pressure CVD method.
The film was formed at 0°C. The film thickness is 1000 people. The gate insulating film 6 is formed by volumetric inert carrier gas 9 by atmospheric pressure CVD method.
For 0%, raw material gas (monosilane gas: oxygen = 4:
3) was flowed at a flow rate of 10% to form a film with a thickness of 1000 at a temperature of 480°C. Gate polycrystalline silicon film 11
The film thickness is 100% under the same conditions as the polycrystalline silicon film number 3.
After forming 0 layers, thermal diffusion of phosphorus was applied to the entire substrate to lower the resistance of the film.
膜は全て連続形成しているため界面の汚染がない。Since all the films are formed continuously, there is no contamination at the interface.
また従来技術で見られたようにカバー用のＣＶＤシリコ
ン酸化膜４の除去がなく、多結晶シリコンＰＩＡ３と絶
縁基板２表面に段差が生じない。次にホトリソグラフィ
ーによって（２）のように島状に堆積層をエッチカット
する。この加工様子を斜視図、第３図にて詳細に説明す
る。第３図（ａ）は。Further, unlike in the prior art, there is no need to remove the CVD silicon oxide film 4 for the cover, and no step is created between the polycrystalline silicon PIA 3 and the surface of the insulating substrate 2. Next, the deposited layer is etched into island shapes as shown in (2) by photolithography. This process will be explained in detail with reference to a perspective view and FIG. Figure 3(a) is.
島状の堆積層にホトレジストパターン５をクロスオーバ
させチャネル部分となる部分をカバーする。A photoresist pattern 5 is crossed over the island-shaped deposited layer to cover a portion that will become a channel portion.
この状態のものでゲート多結晶シリコン膜１１さらにゲ
ート絶縁膜６の順にエツチングカットする。In this state, the gate polycrystalline silicon film 11 and then the gate insulating film 6 are etched and cut in this order.
続いてホトレジストパターン５をマスクに剥出ししてる
多結晶シリコン膜３表面にセルファラインによってイオ
ン打込みし、ソース・ドレイン領域８．９を形成する。Subsequently, using the photoresist pattern 5 as a mask, ions are implanted into the exposed surface of the polycrystalline silicon film 3 using a self-aligning method to form source/drain regions 8.9.
ドーパントにリンを使用し、ドーズ量は、５ Ｘ １０
ｌＢａｍ−”、電圧は、３０ＫｅＶの条件である。次
にレジストパターン５を除去し、イオン打込みしたリン
の活性化処理を不活ガス雰囲気で温度６００’Ｃ，１５
時間する。第３図（ｂ）に素子構造を示す。なおこの構
造は第１図の工程（３）に相当するものである６次に電
極配線をするために層間絶縁膜１２形成をする方法を第
４図で説明する。第４図（、）は第３図（ｂ）における
２点Ａ−Ａ’間を絶縁基板２の表面に垂直に切った図で
ある。まずこの絶縁基板２表面に４０００人厚の層間絶
縁膜１２を形成する。層間絶縁膜１２は常圧ＣＶＤ法に
よるＰ Ｓ Ｇ （ＰｈｏｓｐｈｏｓｉｌｉｃａｔｅＧ
ｌａｓｓ）を採用した。形成条件は不活性キャリアガス
９０％の容積に対し原料ガス（モノシラン：フォスフイ
ン：酸素＝４：１：６）１０％で導入し、温度４８０℃
で形成した。次にコプレーナ型薄膜トランジスタを溝成
する多結晶シリコン上のソース・ドレイン・ゲート部に
コンタクトホール１３゜１４．１５を形成する。次でス
パッタリングによってＡＱ−Ｓｉ（２％）を８０００人
の厚さに形成した後、ホトリソグラフィーによってゲー
ト１６、ソース１７．ドレイン１８の電極パターンを形
成する０以上の結果、第２図（ｂ）および第４図（ｂ）
の断面に見る様な本発明コプレーナ型薄膜トランジスタ
が得られる。なお層間絶縁膜１２としては、ＰＳＧの外
、酸化シリコン膜、窒化シリコン膜、酸化タンタル膜等
が有効果である。Phosphorus is used as a dopant, and the dose is 5 x 10
lBam-", the voltage is 30 KeV. Next, the resist pattern 5 is removed, and the ion-implanted phosphorus is activated at a temperature of 600'C for 15 minutes in an inert gas atmosphere.
Take time. FIG. 3(b) shows the device structure. This structure corresponds to step (3) in FIG. 1. A method of forming an interlayer insulating film 12 for the sixth electrode wiring will be explained with reference to FIG. FIG. 4(,) is a view cut perpendicularly to the surface of the insulating substrate 2 between two points A-A' in FIG. 3(b). First, an interlayer insulating film 12 having a thickness of 4,000 layers is formed on the surface of this insulating substrate 2. The interlayer insulating film 12 is made of PSG (Phosphosilicate G) by normal pressure CVD method.
las) was adopted. The formation conditions were as follows: 10% of the raw material gas (monosilane:phosphine:oxygen = 4:1:6) was introduced to the volume of 90% of the inert carrier gas, and the temperature was 480°C.
It was formed with Next, contact holes 13.degree. 14.15 are formed in the source, drain, and gate portions of the polycrystalline silicon that will form the coplanar thin film transistor. Next, AQ-Si (2%) was formed to a thickness of 8000 nm by sputtering, and then gate 16, source 17. Results of 0 or more forming the electrode pattern of the drain 18, FIG. 2(b) and FIG. 4(b)
A coplanar thin film transistor of the present invention as seen in the cross section is obtained. Note that as the interlayer insulating film 12, in addition to PSG, a silicon oxide film, a silicon nitride film, a tantalum oxide film, etc. are effective.
また多結晶シリコン膜３．ゲート、Ｉｆｉ縁膜６．ゲー
ト多結晶シリコン膜が厚い場合は、第５図に示すように
エツチングによる段差部が大きいので、層間ｌＩＡ縁膜
１２を形成する前に、Ｅ ＣＲ（ｅｌｅｃｔｒｏｎｃｙ
ｃｒｏｔｒｏｎ ｒｅｓｏｎａｎｃｅ ｐｌａｓｍａ）
等により、積層の側面部１９にもシリコン酸化膜２０等
を形成して段差を緩和し、ゲート電極１６の配線を容易
にする６以上の結果、絶縁基板２上のデータ線、ゲート
線の配線が容易になる。Also, polycrystalline silicon film 3. Gate, Ifi membrane6. If the gate polycrystalline silicon film is thick, as shown in FIG.
crotron resonance plasma)
As a result of above 6, the wiring of the data line and gate line on the insulating substrate 2 is made easier by forming a silicon oxide film 20 etc. on the side surface part 19 of the laminated layer to reduce the level difference and facilitate the wiring of the gate electrode 16. becomes easier.
以上の如く本発明はゲート形成領域の多結晶シリコン膜
、ゲート絶縁膜を連続成膜し、工程中の外部汚染から完
全に保護する手段を講じてあり、従来のレジストによる
汚染は全くない、したがってこれまでのレジストを介在
する方法に比べれば格段と向上し非常に信頼性が高く特
性が安定している。また、レジスト工程でシリコン酸化
膜を多結晶シリコン面に当てカバーし、レジストの汚染
から保護する方法が提案されているが欠点とじて製造工
程が増えて繁雑になることである。本発明によれば、コ
プレーナ型薄膜トランジスタの製作において、製作工程
を増やさない簡易プロセスでゲート形成領域の汚染問題
を排除し、セルファライン方式によってすぐれた素子が
できる効果がある。As described above, in the present invention, the polycrystalline silicon film and the gate insulating film in the gate formation region are continuously formed, and measures are taken to completely protect them from external contamination during the process, and there is no contamination caused by the conventional resist. Compared to the conventional method using a resist, this method is much improved and has extremely high reliability and stable characteristics. Furthermore, a method has been proposed in which a silicon oxide film is applied to the polycrystalline silicon surface during the resist process to protect it from contamination, but the drawback is that it increases the number of manufacturing steps and makes it complicated. According to the present invention, in manufacturing a coplanar thin film transistor, the problem of contamination of the gate formation region can be eliminated through a simple process without increasing the number of manufacturing steps, and an excellent device can be produced using a self-line method.
第１図は本発明の一実施例のコプレーナ型薄膜トランジ
スタの製作プロセスの縦断面図、第２図は従来法のコプ
レーナ型薄膜トランジスタの製作プロセスの断面図、第
３図は第１図（２）、（３）の斜視図、第４図（ａ）は
第３図のＡ−Ａ’線断面図、第４図（ｂ）は第４図（ａ
）のプロセスが進行したもので第１図（４）に相当する
図、第５図は第４図（ｂ）の変形図である。
２・・・絶縁基板、３・・・多結晶シリコン膜、６・・
・ゲート絶縁膜、７・・・多結晶シリコン膜、８・・・
ソース領域、９・・・ドレイン領域、１０．１２・・・
層間絶縁膜、１１・・・ゲート多結晶シリコン膜、１６
・・・ゲート電第 １ 口
茅ＺＣ］
＄３ 口
と
２ 洞す撃基柘
３・−・々＃＆Δ）２碌FIG. 1 is a longitudinal sectional view of the manufacturing process of a coplanar thin film transistor according to an embodiment of the present invention, FIG. 2 is a sectional view of the manufacturing process of a conventional coplanar thin film transistor, and FIG. (3) is a perspective view, FIG. 4(a) is a sectional view taken along the line AA' in FIG.
) is a diagram corresponding to FIG. 1(4), and FIG. 5 is a modified diagram of FIG. 4(b). 2... Insulating substrate, 3... Polycrystalline silicon film, 6...
・Gate insulating film, 7... Polycrystalline silicon film, 8...
Source region, 9...Drain region, 10.12...
Interlayer insulating film, 11... Gate polycrystalline silicon film, 16
...Gate Den No. 1 Kuchi Kaya ZC] $3 Kuchi and 2 Tosu Gekiki 柘3...T # & Δ) 2
Claims (1)
した透明絶縁基板上のコプレーナ型トランジスタにおい
て、該透明基板上にソース・ドレイン・チャネル部を設
ける多結晶シリコン膜、ゲート絶縁膜、ゲート電極を連
続形成し、第１のホトリソ工程によつて、該連続形成層
を島状加工する工程と、第２のホトリソ工程によつて、
該加工島の中央のチャネル領域形成部をマスクし、該マ
スク以外のゲート電極膜、ゲート絶縁膜をエッチング除
去し、該チャネル領域を保護して、イオン打込みによる
セルファライン法でソース・ドレイン部に不純物をドー
ピングする工程と、該パターン全領域を層間絶縁膜で被
覆し、ソース・ドレイン・ゲート上の該層間絶縁膜の一
部を除去しソース・ドレイン・ゲートの電極を該透明絶
縁基板上のデータ線とゲート線に配線する工程であるこ
とを特徴とするコプレーナ型トランジスタの製造方法。 ２、特許請求の範囲第１項において、層間絶縁膜として
酸化シリコン、リンシリケートガラス、窒化シリコン膜
、酸化タンタル膜を用いることを特徴とするコプレーナ
型トランジスタの製造方法。 ３、アクティブマトリクスのデータ線とゲート線を搭載
した透明絶縁基板上のコプレーナ型トランジスタにおい
て、該トランジスタのソース・ドレイン・チャネル部と
なる第１の多結晶シリコン層とゲート絶縁膜となるシリ
コン酸化膜層とゲート電極となる第２の多結晶シリコン
層を続けて形成した堆積層であつて島状であり、該トラ
ンジスタのチャネル部となる領域上部の該ゲート絶縁膜
と該第２の多結晶シリコン膜パターンが該第１の多結晶
シリコン層上にのみ同一形状に形成してなり、さらに該
薄膜トランジスタ全領域に層間絶縁膜の被覆層があり、
該トランジスタチャネル部上の該第２の多結晶シリコン
の一部と該トランジスタソースおよびドレイン領域の第
１多結晶シリコン層の不純物ドープ領域上の該層間絶縁
膜の所要の電極コンタクト窓開部を通して、アルミニウ
ムの電極配線が具備されアクティブマトリクスのデータ
線とゲート線を搭載した透明絶縁基板上のコプレーナ型
薄膜トランジスタ。 ４、特許請求の範囲第３項記載の薄膜トランジスタにお
いて、前記層間絶縁膜として酸化シリコン、リンシリケ
ートガラス、窒化シリコン膜および酸化タンタル膜の少
なくとも一種を用いることを特徴とするコプレーナ型ト
ランジスタ。[Claims] 1. In a coplanar transistor on a transparent insulating substrate on which active matrix data lines and gate lines are mounted, a polycrystalline silicon film and a gate insulating film on which source, drain, and channel portions are provided on the transparent substrate. , a step of continuously forming a gate electrode, processing the continuous formed layer into an island shape by a first photolithography step, and a second photolithography step,
The central channel region forming part of the processing island is masked, the gate electrode film and gate insulating film other than the mask are etched away, the channel region is protected, and the source/drain part is formed by self-line method using ion implantation. A process of doping impurities, covering the entire area of the pattern with an interlayer insulating film, removing a part of the interlayer insulating film on the source, drain, and gate, and connecting the source, drain, and gate electrodes to the transparent insulating substrate. A method for manufacturing a coplanar transistor characterized by a step of wiring data lines and gate lines. 2. A method for manufacturing a coplanar transistor according to claim 1, characterized in that silicon oxide, phosphosilicate glass, silicon nitride film, or tantalum oxide film is used as the interlayer insulating film. 3. In a coplanar transistor on a transparent insulating substrate on which active matrix data lines and gate lines are mounted, a first polycrystalline silicon layer that becomes the source, drain, and channel portion of the transistor and a silicon oxide film that becomes the gate insulating film. The deposited layer is formed by successively forming a second polycrystalline silicon layer and a second polycrystalline silicon layer that will become a gate electrode, and is island-shaped, and includes the gate insulating film and the second polycrystalline silicon layer above a region that will become a channel part of the transistor. A film pattern is formed in the same shape only on the first polycrystalline silicon layer, and further there is a covering layer of an interlayer insulating film over the entire region of the thin film transistor,
through a required electrode contact window opening in the interlayer insulating film over a portion of the second polycrystalline silicon layer on the transistor channel portion and an impurity-doped region of the first polycrystalline silicon layer in the transistor source and drain regions; A coplanar thin film transistor on a transparent insulating substrate, equipped with aluminum electrode wiring and equipped with active matrix data lines and gate lines. 4. A coplanar transistor according to claim 3, wherein at least one of silicon oxide, phosphosilicate glass, silicon nitride film, and tantalum oxide film is used as the interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2368688A JPH01200672A (en) | 1988-02-05 | 1988-02-05 | Coplanar transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2368688A JPH01200672A (en) | 1988-02-05 | 1988-02-05 | Coplanar transistor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01200672A true JPH01200672A (en) | 1989-08-11 |
Family
ID=12117329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2368688A Pending JPH01200672A (en) | 1988-02-05 | 1988-02-05 | Coplanar transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01200672A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03184379A (en) * | 1989-12-13 | 1991-08-12 | Toshiba Corp | Manufacture of thin-film transistor |
| JP2001177099A (en) * | 1999-12-14 | 2001-06-29 | Furontekku:Kk | Manufacturing method of thin-film transistor, active matrix substrate, and thin-film deposition device |
| JP2007173803A (en) * | 2006-12-11 | 2007-07-05 | Lg Philips Lcd Co Ltd | Thin film forming device |
-
1988
- 1988-02-05 JP JP2368688A patent/JPH01200672A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03184379A (en) * | 1989-12-13 | 1991-08-12 | Toshiba Corp | Manufacture of thin-film transistor |
| JP2001177099A (en) * | 1999-12-14 | 2001-06-29 | Furontekku:Kk | Manufacturing method of thin-film transistor, active matrix substrate, and thin-film deposition device |
| JP2007173803A (en) * | 2006-12-11 | 2007-07-05 | Lg Philips Lcd Co Ltd | Thin film forming device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR0143542B1 (en) | Method for fabricaiton of semiconductor device having polycrystalline silicon and metal silicides | |
| EP0077737A2 (en) | Low capacitance field effect transistor | |
| US4740482A (en) | Method of manufacturing bipolar transistor | |
| JPH088317B2 (en) | Semiconductor memory device and manufacturing method thereof | |
| JPH01200672A (en) | Coplanar transistor and manufacture thereof | |
| JPH0523056B2 (en) | ||
| JPS6228591B2 (en) | ||
| JP2695812B2 (en) | Semiconductor device | |
| JPH05109983A (en) | Semiconductor device and its manufacture | |
| JPH09270517A (en) | Method of manufacturing thin film transistor | |
| JPH06169082A (en) | Semiconductor device and manufacture thereof | |
| JPH01260857A (en) | Semiconductor device and manufacture thereof | |
| JP3147374B2 (en) | Semiconductor device | |
| KR19980058438A (en) | Silicide Formation Method of Semiconductor Device | |
| JPH0613605A (en) | Semiconductor device and manufacture thereof | |
| JPH04338650A (en) | Semiconductor device and manufacture thereof | |
| JPH0529624A (en) | Thin film transistor and manufacture thereof | |
| JPH07161816A (en) | Semiconductor device | |
| JPS61111573A (en) | Semiconductor device | |
| JPH0563144A (en) | Integrated circuit with thin-film resistor | |
| JPS6120154B2 (en) | ||
| JPH02268443A (en) | Semiconductor device | |
| JPS61248547A (en) | Manufacture of semiconductor device | |
| JPH07240461A (en) | Fabrication of semiconductor device | |
| JPS61147575A (en) | Manufacture of semiconductor device |