JPS5933273B2 - 半導体発光素子の取付け装置 - Google Patents

半導体発光素子の取付け装置

Info

Publication number
JPS5933273B2
JPS5933273B2 JP54013587A JP1358779A JPS5933273B2 JP S5933273 B2 JPS5933273 B2 JP S5933273B2 JP 54013587 A JP54013587 A JP 54013587A JP 1358779 A JP1358779 A JP 1358779A JP S5933273 B2 JPS5933273 B2 JP S5933273B2
Authority
JP
Japan
Prior art keywords
light emitting
semiconductor light
emitting device
device mounting
mounting equipment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54013587A
Other languages
English (en)
Other versions
JPS55105390A (en
Inventor
清 白川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP54013587A priority Critical patent/JPS5933273B2/ja
Publication of JPS55105390A publication Critical patent/JPS55105390A/ja
Publication of JPS5933273B2 publication Critical patent/JPS5933273B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Description

【発明の詳細な説明】 本発明は半導体発光素子の取付け装置に関し、その取付
け高さを任意の高さに選択することができるようにした
ものである。
まず、従来のこの種装置について第１図、第２図を用い
て説明すると、１は半導体発光素子であり、２、３は金
属支持板である。
前記金属支持板２、３はそれぞれが対をなしてその複数
の対が連結板４により予め一体に形成されており、半導
体発光素子１は各金属支持板２、３上で銀ペースト等の
導電性接合材により接合および金線５等を用いてボンデ
ングにより接続されている。６は前記半導体発光素子１
を保護する保護樹脂である。
前記金属支持板２、３は前記半導体発光素子１を保護樹
脂６で保護した後、連結板４をプレス等で切断し、第２
図に示すように独立された金属支持板２、３に半導体発
光素子１が取付けられプこ部品として完成される。
このようにして完成された部品を印刷配線基板等に実装
する際、取付け面から比較的高い位置に５ 半導体発光
素子１を位置させたい場合、金属支持板２、３をフォー
ミング加工したりして位置出しを行なつているが、これ
は非常に手間がかかり、また精度的にも難点があつた。
また連結板の切断突起片４ａをストッパーに利用する方
法も考えら１０れるが、これはその取付け高さが必然的
に決定されてしまうため、半導体発光素子１を任意の高
さに選択することができないため、凡用性がなく、不都
合である。本発明はこのような従来の欠点を解消したも
の１５であり、以下その一実施例について第３図、第４
図を用いて説明する。
第３図、第４図において、第１、２図の従来のものと同
一構成部分には同一番号が附してあり、本発明は予め金
属支持板２、３を複数個の連結板２０Ｔ、８、９、１Ｏ
、１１で連結する。
そして、この連結板Ｔ〜１１の切断時、実装時の条件に
よりその連結板７〜１１の残跡部を例えば第４図ａ、ｂ
に示すように突起片Ｔａとして残すか、ま、た９ａとし
て残すかを選択することによ２５り、この突起片Ｔａ、
９ａをストッパーに利用し、半導体発光素子１の取付け
高さを選択することができるものである。本発明は以上
のように、簡単な構成で半導体発光素子の実装時の取付
け高さを任意の高さに選択３０することができるもので
あり、しかもその高さ位置は金属支持板の連結板の残部
突起片をストッパーに利用するという簡単な手段で設定
され、極めて安価に実施できるという効果を有するもの
である。
【図面の簡単な説明】
第１図は従来例を示す連結板の切断前の状態の一部断面
正面図、第２図は同連結板の切断後の状？を示す一部断
面正面図、第３図は本発明の一実帷例の連結板の切断前
の状態を示す一部断面正面図、第４図Ａ，ｂは同連結板
の切断後の状態をそミす一部断面正面図である。 ・半導体発光素子、２，３・・・・・・金属支持板、・
・・・・・連結板、７ａ９９ａ・・・・・―突起片。

Claims (1)

    【特許請求の範囲】
  1. １ 複数の連結板により一体となつた対をなす複数の金
    属支持板上に半導体発生素子を取付け、かつ前記複数の
    連結板を切断し、その切断による残跡部に突起片を選択
    的に形成することにより前記半導体発光素子の実装高さ
    を選択的に設定可能に構成してなる半導体発光素子の取
    付け装置。
JP54013587A 1979-02-08 1979-02-08 半導体発光素子の取付け装置 Expired JPS5933273B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54013587A JPS5933273B2 (ja) 1979-02-08 1979-02-08 半導体発光素子の取付け装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54013587A JPS5933273B2 (ja) 1979-02-08 1979-02-08 半導体発光素子の取付け装置

Publications (2)

Publication Number Publication Date
JPS55105390A JPS55105390A (en) 1980-08-12
JPS5933273B2 true JPS5933273B2 (ja) 1984-08-14

Family

ID=11837312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54013587A Expired JPS5933273B2 (ja) 1979-02-08 1979-02-08 半導体発光素子の取付け装置

Country Status (1)

Country Link
JP (1) JPS5933273B2 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2809951B2 (ja) * 1992-12-17 1998-10-15 株式会社東芝 半導体発光装置とその製造方法
US6808950B2 (en) 1992-12-17 2004-10-26 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing the device
US6677614B1 (en) 1992-12-17 2004-01-13 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing the device

Also Published As

Publication number Publication date
JPS55105390A (en) 1980-08-12

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