JPS5925387B2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5925387B2
JPS5925387B2 JP55078158A JP7815880A JPS5925387B2 JP S5925387 B2 JPS5925387 B2 JP S5925387B2 JP 55078158 A JP55078158 A JP 55078158A JP 7815880 A JP7815880 A JP 7815880A JP S5925387 B2 JPS5925387 B2 JP S5925387B2
Authority
JP
Japan
Prior art keywords
bonding pad
oxide film
insulating layer
layer
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55078158A
Other languages
English (en)
Other versions
JPS574144A (en
Inventor
明 黒丸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP55078158A priority Critical patent/JPS5925387B2/ja
Priority to GB8116777A priority patent/GB2078442B/en
Priority to DE19813122740 priority patent/DE3122740A1/de
Publication of JPS574144A publication Critical patent/JPS574144A/ja
Publication of JPS5925387B2 publication Critical patent/JPS5925387B2/ja
Priority to US06/649,955 priority patent/US4539582A/en
Expired legal-status Critical Current

Links

Classifications

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明はボンディングパッドを有した半導体装置に関す
る。
従来、例えばＭＯＳ集積回路のボンディングパッドのま
わりの表面構造は、第１図または第２図のようになつて
いる。
即ちＮまたはＰ型基板１を熱酸化して酸化膜（ＳｉＯ２
膜）２を形成し、この膜２にフォトエッチングで拡散用
孔を設け、ここから不純物の選択拡散を行なうことによ
り、基板１とは反対導電型の層３を形成する。次にゲー
ト部分の酸化膜２を除き、ここに改めてゲート酸化膜４
を形成する。その後エッチングで電極取り出し用の孔を
あけ、全面にアルミニウムを蒸着してから該アルミニウ
ムを選択的に除去することにより、電極配線５れボンデ
ィングパッド５２を形成する。次にＣＶＤ法等で表面保
護用のＰＳＧ層６を設け、パッド５２上のＰＳＧ層６は
除去する。その後ボンディングパッド５２の表面に、ボ
ンディングワイヤ先端の金ボールＴを圧着することによ
り、第１図または第２図の構造を得るものである。とこ
ろで上記のような構造であると、基板１上に形成された
熱酸化膜２の厚みは一様であるため、その上に形成され
るアルミニウム配線５１とボンディングパッド５２とは
同一面になるが、配線層５１を含め内部素子をＰＳＧ層
６で保護するデバイスにおいては、ＰＳＧ層６の厚み分
だけボンディングパッド２より上方に突き出ることにな
る。
つまり図示Ａ面よりＢ面の方が上に位置する。しかしな
がら近年にお〜・ては素子構造が縮少化され、ボンディ
ングパッド５２とそれ以外の電極配線５１との間の距離
も短かくする傾向にある。このためボンディング作業に
おいて、金ボール７の中心がパッド５２の中心Ｃからず
れた場合、金ボール７が配線５１土にかぶさつたり、そ
の近傍まで接近するようになり、歩留り低下の要因とな
つていた。即ち配線５１等を保護しているＰＳＧ層６は
、ボンディング等による集中応力（衝撃荷重）に弱いた
め、金ボールＴによる集中心力によつてクラック８が生
じ、その中に金が侵入するとショート不良を起こしてし
まうものである。また近年ボンディングマシンも改良さ
れ、フルオートボンディングが行なわれているが、この
場合ホンデイングパツド５２を光学系で検出し、マウン
トによるずれ量を補正する手段が使用される。この時Ｐ
ＳＧ層６は透明でかつパツド５２と配線５１とが同一平
面上にあるため、前記光学系による光反射角が同一とな
り、誤つてパツド５２の囲りの配線５１を検出してしま
う等の不都合が生じ、誤動作の原因となつていた。本発
明は上記実情に鑑みてなされたもので、ボンデイングパ
ツドと隣接する区域に設けられる導電層の表面保護用絶
縁層の表面を、ボンデイングパツドの表面と同じかまた
はそれより低く位置させることにより、前記従来の問題
点を改善し、近年の素子縮少化にも対処し得る半導体装
置を提供しようとするものである。
以下図面を参照して本発明の一実施例を説明する０まず
第３図に示す如く、Ｎ型またはＰ型基板１上に熱酸化膜
２１を従来より１．５倍程度厚く形成する。
その後選択エツチングで、ボンデイングパツド形成予定
領域以外の熱酸化膜２１を除去し、改めてそれ以外の部
分に酸化膜２１の１／２程度の酸化膜４をＣＶＤ法等で
設ける。それから前述の従来例の場合と同様に酸化膜エ
ツチング→不純物拡散→ゲート酸化膜形成予定領域のエ
ツチング→ゲート酸化膜形成→ゲート酸化膜エツチング
→アルミニウム蒸着→アルミニウム層のエツチング→Ｐ
ＳＧ層形成→ＰＳＧ層のエツチングと工程を進め、金ボ
ール７の圧着工程を行なうが、これらの工程は前述の従
来例の場合と対応するから、対応個所には同一符号を付
して詳しい説明は省略する。上記の如き第３図の構成に
あつては、ボンデイングパツド面（Ａ面）とこれに近接
する電極配線上のＰＳＧ層面（Ｂ面）との間に段差があ
り、ＰＳＧ層６のＢ面の方が低くなつている。
このため金ボール７のボンデイング時の衝撃が伝わりに
くくなり、ボンデイング時の位置ずれが発生しても、シ
ヨート不良とはならない利点がある。また７ルオートボ
ンデイングにおいて、ボンデイングパツド５２を光学系
で検出し、マウントによるずれ量を補正する手段を使用
する場合、ボンデイングパツド５２と電極配線５１の光
反射角を異ならせることができ、従つてボンデイングパ
ツド５２のみをターゲツトとして検出でき、誤動作を防
止できるものである。第４図は本発明の他の実施例であ
る。
１１］ら第３図の実施例では、ＰＳＧ層６の一部をボン
デイングパツド５２の縁部にかぶさるまで延出させてい
るが、第４図では上記ＰＳＧ層６をパツド５２の手前で
止め、またボンデイングパツド面（Ａ面）と電極配線５
１上のＰＳＧ層面（Ｂ面）とを同一平面上に設けている
。
この実施例の場合も、電極配線上のＰＳＧ層６の面がボ
ンデイングパツド面より土方に突出せず、またボンデイ
ングパツド５２と配線５１との間に段差があるので、前
実施例の場合と同様の効果が得られる。なお本発明は上
記実施例のみに限定されるものではなく、例えばＰＳＧ
層６の表面をボンデイングパツド５２の表面と同じかま
たはそれより低く位置させるための他の方法として、酸
化膜２１の形成予定領域にも酸化膜２２を設け、酸化膜
２１の形成予定領域のみ酸化膜を厚くする手法を施こし
てもよい。
また表面保護用絶縁層としてＰＳＧ層６等を用い、また
ボンデイングパツド５２、電極配線５２としてアルミニ
ウムよりなる導電層を用いたが、他の材質よりなる導電
層を用いてもよい等、種々の応用が可能である。以上説
明した如く本発明によれば、ボンデイングパツドと隣接
する区域に設けられる導電層の保護用絶縁層の表面を、
ボンデイングパツド面と同じかまたはそれより低く位置
させたので、ボンデイング時のシヨート不良やボンデイ
ングパツドの位置誤検出が防止でき、従つて素子縮少化
がなされても歩留向上が期待できる半導体装置が得られ
る。
またボンデイングパツド下の絶縁層の厚みを導電層下の
絶縁層の厚みより厚くしたので、ボンデイングパツドと
半導体基板間のリーク及びキャパシタンスを極小に保持
できるものである。
【図面の簡単な説明】
第１図，第２図は従来の半導体装置を示す構成図、第３
図，第４図は本発明の実施例を示す構成図である。 １・・・・・・半導体基板、２１，２２・・・・・・酸
化膜、４・・・・・・ゲート酸化膜、５１・・・・・・
電極配線、５２・・・・・・ボンデイングパツド、６・
・・・・・ＰＳＧ層、７・・・・・・金ボール。

Claims (1)

  1. 【特許請求の範囲】 １ 半導体基板上に絶縁層を介してボンディングパッド
    を設け、前記半導体基板上の前記ボンディングパッドと
    隣接する区域に絶縁層を介して導電層を設け、該導電層
    上の表面を絶縁層で覆い、前記導電層の表面を覆う絶縁
    層の表面を、前記ボンディングパッドの表面と同じかま
    たはそれより低く位置させ、前記ボンディングパッドに
    金ボールを圧着してなり、前記導電層の端部が、前記ボ
    ンディングパッドの端部から前記金ボールの直径の半分
    内に位置することを特徴とする半導体装置。 ２ 導電層下の絶縁層の厚みをボンディングパッド下の
    絶縁層の厚みより薄く形成した特許請求の範囲第１項記
    載の半導体装置。
JP55078158A 1980-06-10 1980-06-10 半導体装置 Expired JPS5925387B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP55078158A JPS5925387B2 (ja) 1980-06-10 1980-06-10 半導体装置
GB8116777A GB2078442B (en) 1980-06-10 1981-06-02 A semiconductor device bonding pad
DE19813122740 DE3122740A1 (de) 1980-06-10 1981-06-09 Halbleiterbauelement
US06/649,955 US4539582A (en) 1980-06-10 1984-09-11 Anti-short bonding pad structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55078158A JPS5925387B2 (ja) 1980-06-10 1980-06-10 半導体装置

Publications (2)

Publication Number Publication Date
JPS574144A JPS574144A (en) 1982-01-09
JPS5925387B2 true JPS5925387B2 (ja) 1984-06-16

Family

ID=13654105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55078158A Expired JPS5925387B2 (ja) 1980-06-10 1980-06-10 半導体装置

Country Status (4)

Country Link
US (1) US4539582A (ja)
JP (1) JPS5925387B2 (ja)
DE (1) DE3122740A1 (ja)
GB (1) GB2078442B (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0724276B2 (ja) * 1988-02-05 1995-03-15 三菱電機株式会社 ワイヤボンデイングパッドの組立体
US6555757B2 (en) * 2000-04-10 2003-04-29 Ngk Spark Plug Co., Ltd. Pin solder jointed to a resin substrate, made having a predetermined hardness and dimensions

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1099930A (en) * 1966-05-31 1968-01-17 Fairchild Camera Instr Co Improvements in or relating to semiconductor devices
US3717567A (en) * 1967-05-29 1973-02-20 A Bodine Use of sonic resonat energy in electrical machining
NL159822B (nl) * 1969-01-02 1979-03-15 Philips Nv Halfgeleiderinrichting.
US3721838A (en) * 1970-12-21 1973-03-20 Ibm Repairable semiconductor circuit element and method of manufacture
JPS5028763A (ja) * 1973-07-13 1975-03-24
DE2348323A1 (de) * 1973-09-26 1975-04-03 Licentia Gmbh Integrierte festkoerperschaltung mit einer vielzahl von bauelementen in einem gemeinsamen halbleiterkoerper
US4188438A (en) * 1975-06-02 1980-02-12 National Semiconductor Corporation Antioxidant coating of copper parts for thermal compression gang bonding of semiconductive devices
JPS5851425B2 (ja) * 1975-08-22 1983-11-16 株式会社日立製作所 ハンドウタイソウチ
JPS583380B2 (ja) * 1977-03-04 1983-01-21 株式会社日立製作所 半導体装置とその製造方法
JPS53123074A (en) * 1977-04-01 1978-10-27 Nec Corp Semiconductor device
JPS5918870B2 (ja) * 1977-05-15 1984-05-01 財団法人半導体研究振興会 半導体集積回路
DE2727319A1 (de) * 1977-06-16 1979-01-04 Nippon Electric Co Halbleiteranordnung mit einer hoeckerfoermigen anschlusselektrode
JPS5459080A (en) * 1977-10-19 1979-05-12 Nec Corp Semiconductor device
NL184549C (nl) * 1978-01-27 1989-08-16 Philips Nv Halfgeleiderinrichting voor het opwekken van een elektronenstroom en weergeefinrichting voorzien van een dergelijke halfgeleiderinrichting.
JPS54139374A (en) * 1978-04-21 1979-10-29 Toshiba Corp Semiconductor device
US4228447A (en) * 1979-02-12 1980-10-14 Tektronix, Inc. Submicron channel length MOS inverter with depletion-mode load transistor
JPS5745259A (en) * 1980-09-01 1982-03-15 Hitachi Ltd Resin sealing type semiconductor device

Also Published As

Publication number Publication date
GB2078442A (en) 1982-01-06
DE3122740A1 (de) 1982-03-18
GB2078442B (en) 1985-05-30
US4539582A (en) 1985-09-03
DE3122740C2 (ja) 1988-10-20
JPS574144A (en) 1982-01-09

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