JPS59211244A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59211244A JPS59211244A JP8607983A JP8607983A JPS59211244A JP S59211244 A JPS59211244 A JP S59211244A JP 8607983 A JP8607983 A JP 8607983A JP 8607983 A JP8607983 A JP 8607983A JP S59211244 A JPS59211244 A JP S59211244A
- Authority
- JP
- Japan
- Prior art keywords
- film
- pattern
- substrate
- insulating film
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に関し、特に素子分離用
の絶縁膜の形成方法に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming an insulating film for element isolation.
従来、半導体基板としてシリコン基板を用いたＭＯ８半
導体装置では素子分離法として選択酸化灰が最もよく用
いられている。しかし、選択酸化法では素子分離膜の端
部に発生するバーズビークが素子領域の寸法を小さくす
る原因となシ、予めホトマスク上でこの寸法変換差を採
っておかなければならないため、素子の高集積化の妨げ
となっている。Conventionally, selective oxidation ash has been most often used as an element isolation method in MO8 semiconductor devices using a silicon substrate as a semiconductor substrate. However, in the selective oxidation method, bird's beaks generated at the edges of the device isolation film reduce the dimensions of the device region, and this dimensional conversion difference must be measured on the photomask in advance, which makes it difficult to integrate devices with high density. This is hindering the development of
そこで、最近では選択酸化法に代わる素子分離技術とし
て例えばＢＯＸ法が開発されている。Therefore, recently, for example, the BOX method has been developed as an element isolation technique to replace the selective oxidation method.
このＢＯＸ法はシリコン基板をエツチングして溝を形成
し、この溝内に酸化膜を埋設する方法であシ、バーズビ
ークの発生を考慮に入れる必要はない。しかし、この方
法ではシリコン基板を選択的にエツチングして溝を形成
する際、マスク材としてホトレジスト・ぐターンを用い
て転写されたシリコンに対して選択エツチング性を有す
る被膜パターン（例えばＡｔ膜パターン）を用いるため
、写真蝕刻法の限界による制約を受ける。例えば、現在
の紫外線による写真蝕刻法ではホトレゾストパターン間
の間隔が１μｍ以下となるようにホトレジストをパター
ニングすることは非常に困難であるため、微細な素子分
離膜を形成することも困難となっている。This BOX method is a method in which a silicon substrate is etched to form a groove and an oxide film is buried in the groove, and there is no need to take the occurrence of bird's beak into account. However, in this method, when forming grooves by selectively etching a silicon substrate, a film pattern (for example, an At film pattern) that has selective etching properties with respect to the transferred silicon is used as a mask material. Because this method uses a method of photolithography, it is subject to limitations due to the limitations of photolithography. For example, with the current photolithography method using ultraviolet rays, it is extremely difficult to pattern photoresist so that the spacing between photoresist patterns is 1 μm or less, making it difficult to form fine device isolation films. ing.
本発明は上記事情に鑑みてなされたものであシ、従来の
素子分離技術では形成することが困難な１μｍ以下の微
細な素子分離膜を形成して素子の高集積化を達成し得る
半導体装置の製造方法を提供しようとするものである。The present invention has been made in view of the above circumstances, and is a semiconductor device capable of achieving high integration of elements by forming a fine element isolation film of 1 μm or less, which is difficult to form using conventional element isolation techniques. The present invention aims to provide a method for manufacturing.
本発明の半導体装置の製造方法は、まず半導体基板上に
第１の絶縁膜（例えば酸化膜）を形成し、この上に被膜
（例えば多結晶シリコン膜）を堆積した後、この被膜上
にマスク材パターン（例えばホトレジストパターン）を
形成シ、これをマスクとして被膜を等方的にエツチング
してサイドエツチングによりマスク材パターンよシ寸法
の小さい被膜・２ターンを形成する。次に、マスク材ノ
４ターンを残存させた状態で全面に金属膜を蒸着し７だ
後、リフトオフ法によシマスフ膜パターンとその上の金
属膜を除去し、第１の絶縁膜上に金属膜パターンを形成
する。つづいて、前記被膜パターン及び金属膜ノＲター
ンをマスクとして第１の絶縁膜及び基板を順次異方性エ
ツチングによシエッチングして基板内に溝を形成する。In the method for manufacturing a semiconductor device of the present invention, first, a first insulating film (for example, an oxide film) is formed on a semiconductor substrate, a film (for example, a polycrystalline silicon film) is deposited on this film, and then a mask is placed on the film. A material pattern (for example, a photoresist pattern) is formed, and using this as a mask, the film is isotropically etched to form two turns of a film smaller in size than the mask material pattern by side etching. Next, a metal film is vapor-deposited on the entire surface with four turns of the mask material remaining, and after 7 days, the striped film pattern and the metal film on it are removed by a lift-off method, and a metal film is deposited on the first insulating film. Form a film pattern. Subsequently, the first insulating film and the substrate are sequentially etched by anisotropic etching using the coating pattern and the R-turn of the metal film as a mask to form a groove in the substrate.
つづいて、前記被膜パターン及び金属膜パターンを除去
し、全面に第２の被膜を堆積した後、エッチバック法に
よシ基板の溝内に第２の被膜を埋設する。Subsequently, the coating pattern and the metal film pattern are removed, a second coating is deposited on the entire surface, and then the second coating is buried in the groove of the substrate by an etch-back method.
こうした方法によれば、被膜パターンと金属膜パターン
との間には被膜の等方性エツチング時のサイドエツチン
グ分の間隔があシ、これらをマスクとする異方性エツチ
ングにより基板内に前記サイドエツチングに対応する幅
の溝を形成することができる。したがって、この溝内に
第２の絶縁膜を埋設することによシ微細な素子分離膜を
形成することができる。According to this method, there is a gap between the film pattern and the metal film pattern corresponding to side etching during isotropic etching of the film, and by anisotropic etching using these as a mask, the side etching is etched into the substrate. It is possible to form a groove with a width corresponding to the width of the groove. Therefore, by burying the second insulating film in this trench, a fine element isolation film can be formed.
以下、本発明の実施例を第１図〜第８図を参照して説明
する。Embodiments of the present invention will be described below with reference to FIGS. 1 to 8.
（１）まず、Ｐ型シリコン基板１表面に厚さｉ ０００
Ｘの熱酸化膜２を形成した後、この熱酸化膜２上にＣ’
／Ｄ法によシ厚さ５０００Ｘの多結晶シリコン膜３を堆
積する。この多結晶シリコン膜３の膜厚は最終的に形成
される素子分離膜の幅とほぼ等しくなるので、重要な設
定条件となる。（第１図図示）。次に、この多結晶シリ
コン膜３上に写真蝕刻法によりホトレジストパターン４
を形成した後、プラズマエツチング法によυ多結晶シリ
コン膜３を等方的にエツチングする。この等方性エツチ
ングによシサイドエッチングが生じ、ホトレジストパタ
ーン４の端部から約０．５μｍ後退した、ホトレゾスト
パターン４よシ寸法の小さい多結晶シリコン膜パターン
３′が形成される（第２図図示）。(1) First, a thickness of i 000 is applied to the surface of the P-type silicon substrate 1.
After forming the thermal oxide film 2 of X, C' is formed on this thermal oxide film 2.
A polycrystalline silicon film 3 having a thickness of 5000× is deposited by the /D method. The thickness of this polycrystalline silicon film 3 is approximately equal to the width of the element isolation film to be finally formed, and is therefore an important setting condition. (Illustrated in Figure 1). Next, a photoresist pattern 4 is formed on this polycrystalline silicon film 3 by photolithography.
After forming the polycrystalline silicon film 3, the polycrystalline silicon film 3 is isotropically etched by a plasma etching method. This isotropic etching causes side etching, and a polycrystalline silicon film pattern 3' that is smaller in size than the photoresist pattern 4 and is recessed by about 0.5 μm from the edge of the photoresist pattern 4 is formed. (See Figure 2).
（ｉｉ） 次いで、ホトレジスト・クターン４を残存
させた状態で真空蒸着法によシ全面に厚さ１０００Ｘの
Ａｔ膜５を蒸着する。この際、ホトレジストパターン４
の厚さが１μｍ以上あるため、ホトレジストパターン４
上のａ膜５と熱酸化膜２上のＡｔ膜５とは分断されてい
る（第３図図示）。つづいて％０２アッシングあるいは
化学薬品等でホトレジストパターン４を除去し、このホ
トレジストパターン４上のＡ／＝膜５をリフトオフする
。(ii) Next, with the photoresist pattern 4 remaining, an At film 5 having a thickness of 1000× is deposited on the entire surface by vacuum deposition. At this time, the photoresist pattern 4
Since the thickness of photoresist pattern 4 is 1 μm or more,
The upper A film 5 and the At film 5 on the thermal oxide film 2 are separated (as shown in FIG. 3). Subsequently, the photoresist pattern 4 is removed by %02 ashing or chemicals, and the A/= film 5 on the photoresist pattern 4 is lifted off.
この結果、熱酸化膜２上にＡ／＝膜パターン５′が形成
される（第４図図示）。As a result, an A/= film pattern 5' is formed on the thermal oxide film 2 (as shown in FIG. 4).
（ｉｉｉ） 次いで、多結晶シリコン膜ノｆターン３
′及びＡＡ膜・やターフ５′をマスクとして熱酸化膜２
を異方性エツチングによシエッチングし、更に基板１も
異方性エツチングによシ深さ約６０００ ｉまでエツチ
ングする。この結果、基板１内に幅約０５μｍの溝６が
形成される。！た、多結晶シリコン膜パター゛７３′は
基板１の異方性エツチングと同時にエツチング除去され
る（第５図図示）。(iii) Next, polycrystalline silicon film f-turn 3
' and AA film/turf 5' as a mask to form thermal oxide film 2.
is etched by anisotropic etching, and the substrate 1 is also etched by anisotropic etching to a depth of about 6000 m. As a result, a groove 6 having a width of about 05 μm is formed in the substrate 1. ! Furthermore, the polycrystalline silicon film pattern 73' is removed by etching simultaneously with the anisotropic etching of the substrate 1 (as shown in FIG. 5).
つづいて、硫酸と過酸化水素水との混合液あるいは王水
等によＩ） Ａｔ膜パターン５′を除去した後、全面に
厚さ約５０００ＸのＢＳＧ膜（Ｂｏｒｏｎ Ｓｔ ｌ
１ｃａｔｅＧｌ ａｓ ｓ膜）７を堆積する（第６図図
示）。つづいて、異方性エツチングによ、９ ＢＳＧＳ
２Ｏ２ッチパックして、基板１の溝６内にＢＳＧＳ２Ｏ
２部を埋設し、幅約０．５μｍの素子分離膜８を形成す
る。この異方性エツチングによシ前記熱酸化膜２も同時
に除去される（第７図図示）。つづいて、ドライ０２中
１ｏｏｏ℃で１時間熱処理を行ない、素子分離膜８から
ボロンを拡散させてＰ−型フィールド反転防止層９を形
成する。この際、基板１表面には熱酸化膜ノ。が形成さ
れる（第８図図示）。Next, after removing the At film pattern 5' using a mixture of sulfuric acid and hydrogen peroxide solution or aqua regia, a BSG film (Boron St.
1cateGlass film) 7 is deposited (as shown in FIG. 6). Next, by anisotropic etching, 9 BSGS
2O2 patch pack and place BSGS2O in groove 6 of substrate 1.
The second part is buried to form an element isolation film 8 having a width of about 0.5 μm. By this anisotropic etching, the thermal oxide film 2 is also removed at the same time (as shown in FIG. 7). Subsequently, heat treatment is performed at 100 DEG C. for 1 hour in dry 02 to diffuse boron from the element isolation film 8 to form a P-type field inversion prevention layer 9. At this time, a thermal oxide film is formed on the surface of the substrate 1. is formed (as shown in Figure 8).
以下、通常の工程に従い、素子分離膜８によって囲まれ
た素子領域に例えばＭＯ８半導体装置を形成する。Thereafter, an MO8 semiconductor device, for example, is formed in the element region surrounded by the element isolation film 8 according to a normal process.
しかして、上記方法によれば第２図図示の工程でホトレ
ソストノ母ターン４をマスクとして多結晶シリコン膜２
をプラズマエツチング法によシ等方的にエツチングする
際のサイドエツチングによシホトレソストパターン４の
端部から約０．５μｍ後退した寸法の小さい多結晶シリ
コン膜パターン３′を形成することができる。次いで、
第３図図示の工程においてＡ／、膜５を蒸着し、第４図
図示の工程においてリフトオフ法を用いてＡｔ膜パター
ン５′を形成スると、Ａｔｉ／母ターン５′と多結晶シ
リコン膜パターン３′との間には前述したサイドエツチ
ングによる約０．５１ｔｒｎの間隔ができる。次いで、
第５図図示の工程で多結晶シリコン膜パターン３′とＡ
Ｊａ膜／ｆターンダをマスクとして異方性エツチングを
行なうと、基板ｌに幅約０．５μｍの溝６ができる。次
いで、第６図図示の工程におけるＢＳＧＳ２Ｏ２積と、
第７図図示の工程におけるエッチバッグ法によシ幅約０
．５μｍの素子分離膜８を形成できる。このように従来
の選択酸化法やＢＯＸ法では達成できなかった幅１μｍ
以下の素子分離膜８を形成することができ。According to the above method, in the process shown in FIG.
By side etching when etching isotropically by plasma etching method, it is possible to form a small polycrystalline silicon film pattern 3' that is set back about 0.5 μm from the edge of the photoresist pattern 4. . Then,
In the step shown in FIG. 3, the A/film 5 is deposited, and in the step shown in FIG. 4, an At film pattern 5' is formed using the lift-off method. A gap of about 0.51 trn is created between the pattern 3' and the pattern 3' due to the side etching described above. Then,
In the process shown in FIG. 5, polycrystalline silicon film pattern 3' and A
When anisotropic etching is performed using the Ja film/f turner as a mask, a groove 6 with a width of about 0.5 μm is formed in the substrate l. Next, the BSGS2O2 product in the process shown in FIG.
The width is approximately 0 by the etch bag method in the process shown in Figure 7.
．． An element isolation film 8 having a thickness of 5 μm can be formed. In this way, a width of 1 μm could not be achieved using conventional selective oxidation methods or BOX methods.
The following element isolation film 8 can be formed.
しかもこの素子分離膜８０幅を多結晶シリコン膜３の膜
厚で制御することができるので、素子の高集積化にとっ
て多大の効果を得ることができる。Moreover, since the width of the element isolation film 80 can be controlled by the thickness of the polycrystalline silicon film 3, a great effect can be obtained for higher integration of elements.
また、従来のＢＯＸ法ではフィールド反転防止層を形成
するために、基板に設けられた溝の領域にイオン注入を
行なっていたので、溝の側壁へのイオン注入が困難であ
ったが、上記方法では第８図図示の工程で熱処理により
ＢＳＧ膜からなる素子分離膜８からゼロンを拡散させる
ので。In addition, in the conventional BOX method, in order to form a field reversal prevention layer, ions were implanted into the groove region provided in the substrate, making it difficult to implant ions into the sidewalls of the groove. Now, in the step shown in FIG. 8, zero is diffused from the element isolation film 8 made of the BSG film by heat treatment.
自己整合的にフィールド反転防止層９を形成することが
できる。The field inversion prevention layer 9 can be formed in a self-aligned manner.
なお、上記実施例では被膜として多結晶シリコン膜３を
用いたが、これに限らず例えばシリコン窒化膜を用いて
もよい。シリコン窒化膜を用いた場合、第５図図示の工
程に対応する異方性エツチングの工程の後、熱リン酸等
のエツチング液によりシリコン窒化膜パターンを除去す
ればよい。In addition, although the polycrystalline silicon film 3 was used as the film in the above embodiment, the film is not limited to this, and for example, a silicon nitride film may be used. When a silicon nitride film is used, the silicon nitride film pattern may be removed using an etching solution such as hot phosphoric acid after an anisotropic etching step corresponding to the step shown in FIG.
また、上記実施例では金属膜としてＡ／、膜５を用いた
が、これに限らず高融点金属、例えばＴｉ。Further, in the above embodiment, A/, film 5 was used as the metal film, but the invention is not limited to this, and a high melting point metal such as Ti may be used.
Ｍｏ、Ｗ等を用いてもよい。Mo, W, etc. may also be used.
また、第７図図示の工程におけるエツチノ々ツク法では
上記実施例のように８８Ｇ膜７を直接エッチバックする
方法に限らず、 ＢＳＧ膜７上に例えば？リメチルメタ
クリレートとフェノール樹脂からなるレゾスト膜を塗布
した後、異方性エツチングを行なうことにより、素子分
離膜８の上面をより平坦化する方法もある。Furthermore, the etching method in the process shown in FIG. 7 is not limited to the method of directly etching back the 88G film 7 as in the above embodiment, but also etching back the 88G film 7, for example. Another method is to apply anisotropic etching after applying a resist film made of remethyl methacrylate and phenol resin, thereby making the upper surface of the element isolation film 8 more planar.
また、第８図図示の工程における熱処理は温度、界囲気
ガスの種類を任意に設定できることはいうまでもない。Furthermore, it goes without saying that the temperature and type of surrounding gas for the heat treatment in the process shown in FIG. 8 can be set arbitrarily.
更に、本発明方法はＭＯ８半導体装置に限らずバイポー
ラ半導体装置にも同様に適用できることは勿論である。Furthermore, it goes without saying that the method of the present invention can be applied not only to MO8 semiconductor devices but also to bipolar semiconductor devices.
以上詳述した如く、本発明の半導体装置の製造方法によ
れば、１μｍ以下の幅を有する微細な素子分離膜を形成
することができ、素子の高集積化を達成できる等顕著な
効果を奏するものである０As detailed above, according to the method for manufacturing a semiconductor device of the present invention, it is possible to form a fine device isolation film having a width of 1 μm or less, and it has remarkable effects such as achieving high integration of devices. 0 that is a thing
第１図〜第８図は本発明の実施例における素子分離膜を
形成する方法を示す断面図である。
１・・・Ｐ型シリコン基板、２・・・熱酸化膜、３・・
・多結晶シリコン膜、３′・・・多結晶シリコン膜・ぞ
ターン、４・・・ホトレソストパターン、５・・・ｈｔ
Ｈｚ、５′・・・Ａｔ、Ｈパターン、６・・・溝、７
・・・ＢｓＧ膜、８・・・素子分離膜、９・・・フィー
ルド反転防止層、１０・・・熱酸化膜。
出願人代理人 弁理士 鈴 江 武 彦デー
で−、−寸
の
ｑフ琺 悸 恍
区 区
ト Ｏり
派 法1 to 8 are cross-sectional views showing a method of forming an element isolation film in an embodiment of the present invention. 1...P-type silicon substrate, 2...thermal oxide film, 3...
・Polycrystalline silicon film, 3'...Polycrystalline silicon film, turn, 4...Photoresist pattern, 5...ht
Hz, 5'...At, H pattern, 6...groove, 7
...BsG film, 8... Element isolation film, 9... Field inversion prevention layer, 10... Thermal oxidation film. Applicant's Representative Patent Attorney Takehiko Suzue
de-,-sun
of
qfu 琺
Claims (2)
絶縁膜上に被膜を堆績する工程と、該被膜上にマスク材
・母ターンを形成し、これをマスクとして該被膜を等方
性工、チングにょシエッチングしてマスク材ノソターン
より寸法の小さい被膜パターンを形成する工程と、該マ
スク材ノ（り〜ンを残存させた状態で全面に金属膜を蒸
着する工程と、前記マスク材ツクターンを除去し、マス
ク材）等ターン上の金属膜をり７トオフして前記第１の
絶縁膜上に金属膜パターンを形成する工程と、前記被膜
・母ターン及び金属膜・母ターンをマスクとして前記第
１の絶縁膜及び基板の一部を異方性工、チングによシ順
次エツチングして基板内に溝を形成する工程と、前記被
膜ノゼターン及び金属膜パターンを除去した後、全面に
第２の絶縁膜を堆積する工程と、エッチバック法により
前記基板の溝内に第２の絶縁膜を埋設する工程とを具備
したことを特徴とする半導体装置の製造方法。(1) A step of forming a first insulating film on a semiconductor substrate and depositing a film on the first insulating film, forming a mask material/mother turn on the film, and using this as a mask to deposit a film on the first insulating film. A process of isotropically etching the film to form a film pattern smaller in size than the pattern of the mask material, and a process of vapor depositing a metal film over the entire surface with the mask material remaining. a step of removing the mask material turn and removing the metal film on the mask material turn to form a metal film pattern on the first insulating film; and forming a metal film pattern on the first insulating film; - Using the mother turn as a mask, the first insulating film and a part of the substrate are sequentially etched by anisotropic etching and etching to form a groove in the substrate, and the film nose turn and metal film pattern are removed. A method for manufacturing a semiconductor device, comprising the steps of: depositing a second insulating film over the entire surface; and embedding the second insulating film in a groove of the substrate by an etch-back method.
基板の溝内に該第２の絶縁膜を埋設した後、熱処理によ
シ基板中に不純物を拡散させることを特徴とする特許請
求の範囲第１項記載の半導体装置の製造方法。(2) the second insulating film contains impurities of the same conductivity type as the substrate;
2. The method of manufacturing a semiconductor device according to claim 1, wherein after embedding the second insulating film in the groove of the substrate, impurities are diffused into the substrate by heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8607983A JPS59211244A (en) | 1983-05-17 | 1983-05-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8607983A JPS59211244A (en) | 1983-05-17 | 1983-05-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59211244A true JPS59211244A (en) | 1984-11-30 |
Family
ID=13876695
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8607983A Pending JPS59211244A (en) | 1983-05-17 | 1983-05-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59211244A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002057318A (en) * | 2000-08-07 | 2002-02-22 | Sony Corp | Solid-state image sensing element and its manufacturing method |
-
1983
- 1983-05-17 JP JP8607983A patent/JPS59211244A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002057318A (en) * | 2000-08-07 | 2002-02-22 | Sony Corp | Solid-state image sensing element and its manufacturing method |
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