JPS59202648A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59202648A JPS59202648A JP7620083A JP7620083A JPS59202648A JP S59202648 A JPS59202648 A JP S59202648A JP 7620083 A JP7620083 A JP 7620083A JP 7620083 A JP7620083 A JP 7620083A JP S59202648 A JPS59202648 A JP S59202648A
- Authority
- JP
- Japan
- Prior art keywords
- nitride film
- oxide film
- film
- region
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
この発明は、酸化膜分離構造を持つ半導体集積回路装置
において分離用酸化膜全形成する半導体装置の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a semiconductor device in which an isolation oxide film is entirely formed in a semiconductor integrated circuit device having an oxide film isolation structure.
（従来技術）
半導体集積回路装置の製造において、分離領域を酸化膜
に、ｃり形成する方法（以後、酸化膜分離と記す）は分
離領域をＰＮ接合により形成する方法（以後、ＰＮ分離
と記す）と比較して集積度を上げかつ寄生容量を減じる
効果があることが知られている。(Prior art) In the manufacture of semiconductor integrated circuit devices, a method of forming an isolation region in an oxide film (hereinafter referred to as oxide film isolation) is a method in which an isolation region is formed by a PN junction (hereinafter referred to as PN isolation). ) is known to have the effect of increasing the degree of integration and reducing parasitic capacitance.
集積度が上げられる理由としては、分離用酸化膜形成時
に、トランジスタ抵抗などの素子の動作に必要な領域以
外にすべて厚い酸化ｉｔ影形成るため、以後、前記各領
域に不純物を拡散形成する際に厳密なマスク合せが要求
されな−自己整合技術を用いることができるからである
。The reason why the degree of integration is increased is that when forming the isolation oxide film, a thick oxide shadow is formed in all areas other than those necessary for the operation of elements such as transistor resistors. does not require strict mask alignment - self-alignment techniques can be used.
また、寄生容量が減じられる理由としては、トランジス
タ、抵抗などの素子がすべて絶縁物で囲まれるため、各
素子の動作に必要な領域以外の寄生容量の原因となる余
分な接合を減少させることができる。In addition, the reason why parasitic capacitance is reduced is because all elements such as transistors and resistors are surrounded by insulators, which reduces unnecessary junctions that cause parasitic capacitance in areas other than those required for the operation of each element. can.
また集積度を上げることにより配線層全形成させること
が可能なため、配線領域での寄生容量を減少させること
ができるからである。In addition, by increasing the degree of integration, it is possible to form all wiring layers, thereby reducing parasitic capacitance in the wiring region.
このように戚化膜分離金用いれば、従来ＰＮ分離で得ら
れていた素子間隔全縮小して、集積度を上げることおよ
び寄生容量全滅じることについては大きな効果が上がっ
ている。In this way, the use of a dielectric film separation layer has a great effect in completely reducing the element spacing, increasing the degree of integration, and completely eliminating parasitic capacitance, which was previously achieved with PN isolation.
従来の選択酸化法による分離用酸化膜領域の形成方法を
具体的に説明したものが第１図である。FIG. 1 specifically explains a method of forming an isolation oxide film region by a conventional selective oxidation method.
まず、第１図（ａｌに示すように、シリコン基＠１に緩
衝用酸化膜２を形成し、さらに、窒化シリコン膜（以後
、窒化膜と記す）３を堆積する。First, as shown in FIG. 1 (al), a buffer oxide film 2 is formed on a silicon base @1, and then a silicon nitride film (hereinafter referred to as a nitride film) 3 is deposited.
その後、同じく第１図（ａ）に示すように、窒化膜３の
分離酸化膜全形成すべき領域に開口４を設け、この間口
４を介して緩衝用酸化膜２おＬひシリコン基板１をエツ
チングして溝５を形成する。この溝５は分離酸化膜を形
成する際、酸化物の体積の増大が起こるので、酸化処理
後の基体がほぼ平坦となるように設けである１、
しかる後、窒化膜３全マスクとして、シリコン基板１全
は化処理することに、Ｃジ、第１図（ｂ）に示すような
分離用酸化膜領域６を得ることができる。Thereafter, as similarly shown in FIG. 1(a), an opening 4 is provided in the region of the nitride film 3 where the isolation oxide film is to be entirely formed, and the buffer oxide film 2 and the silicon substrate 1 are inserted through this opening 4. Grooves 5 are formed by etching. Since the volume of the oxide increases when forming the isolation oxide film, this groove 5 is provided so that the substrate after oxidation treatment becomes almost flat. By subjecting the entire substrate 1 to a chemical treatment, an isolation oxide film region 6 as shown in FIG. 1(b) can be obtained.
酸化処理の際、酸化は縦方向ばかりでなく横方向にも進
行し、特に緩衝用酸化膜２中ではオキシダントの拡散速
度が太きいために、窒化膜３の下の横方向酸化の進行が
速く、バーズビークとよばれる酸化膜領域７が形成され
る。During oxidation treatment, oxidation progresses not only in the vertical direction but also in the lateral direction, and since the diffusion rate of the oxidant is particularly high in the buffer oxide film 2, the lateral oxidation progresses quickly under the nitride film 3. , an oxide film region 7 called a bird's beak is formed.
その後、窒化膜３を除去し、さらに緩衝用酸化膜２を除
去することにニジ、第１図（ｃ）に示すような分離用ば
化膜領域６全得ることができる。Thereafter, by removing the nitride film 3 and further removing the buffer oxide film 2, the entire isolation oxide film region 6 as shown in FIG. 1(c) can be obtained.
以上のように、従来の選択酸化法にＬる分離用酸化膜領
域６の形成方法では、横方向への酸化が進行するため、
デバイスの動作上、全く不必要なバーズビーク領域の形
成を避けることができない。As described above, in the method of forming the isolation oxide film region 6 using the conventional selective oxidation method, oxidation progresses in the lateral direction.
Formation of a completely unnecessary bird's beak region cannot be avoided in terms of device operation.
一方、近年デバイスの高集積化、高性能化の要求はます
ます強く、素子の微細化全史に進める必要がある。この
ような要求に対して微細パターン形成技術の技術開発は
盛んに行なわれ、現在では１μレベルの微細パターン形
成も実用化されている。On the other hand, in recent years there has been an increasingly strong demand for higher integration and higher performance of devices, and it is necessary to advance the entire history of element miniaturization. In response to such demands, technical development of fine pattern forming techniques has been actively carried out, and at present, fine pattern formation on the 1 micron level has been put into practical use.
このような微細パターン形成技術を駆使した場合、デバ
イスの活性領域については、ノリ一ン寸法通りの微細化
がほぼ可能であるが、分離領域については従来の選択酸
化法を用いる限り、平面的パターン寸法に無関係にバー
ズビーク領域が形成されるため、・ぐターン寸法通りの
微細化は不可能である。When making full use of such fine pattern formation technology, it is almost possible to miniaturize the active region of a device to the exact dimensions, but for the isolation region, as long as conventional selective oxidation methods are used, a planar pattern is possible. Since a bird's beak region is formed regardless of the dimensions, it is impossible to miniaturize the pattern according to the dimensions.
したがって、活性領域に対する分離領域の面積比はパタ
ーンの微細化に伴な−増太し、従来の選択酸化法では、
バーズビークの形成がデ゛バイスの微細化に限界金与え
ることになる、
その他にも、バーズビーク領域の存在はウォールドエミ
ッタ型トランジスタのエミッターコレクタ間短絡を引き
起こし易いなど、素子の特性上も好ましくない。Therefore, the area ratio of the isolation region to the active region increases as the pattern becomes finer, and in the conventional selective oxidation method,
The formation of a bird's beak places a limit on device miniaturization.In addition, the presence of a bird's beak region is undesirable in terms of device characteristics, such as easily causing emitter-collector short circuits in walled emitter transistors.
また、熱成長酸化物の突出物６ａは基板表面に平坦化し
た配線層全形成することが困難にする。In addition, the thermally grown oxide protrusions 6a make it difficult to form a complete wiring layer on the substrate surface.
以上のように、従来の選択酸化法では、バーズビーク領
域の形成が大きな問題点であり、今後、デバイスの高集
積化、高性能化を進めるためには、バーズビークの形成
されない分離領域の形成技術を開発することが必要であ
る。As described above, the formation of bird's beak regions is a major problem with conventional selective oxidation methods, and in order to promote higher integration and higher performance of devices in the future, technology for forming isolation regions that do not form bird's beaks will be developed. It is necessary to develop.
（発明の目的）
この発明は、上記の点に鑑みなされたもので、分離用酸
化膜領域全形成する選択慮化の際に、結晶欠陥を発生さ
せることなくバーズビーク領域の形成を防止することが
でき、分離領域を縮少してデバイスの微細化全可能にす
ることができる半導体装置の製造方法を提供することを
目的とする。(Object of the Invention) The present invention has been made in view of the above points, and it is possible to prevent the formation of bird's beak regions without generating crystal defects when forming the entire isolation oxide film region. An object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the isolation region and completely miniaturize the device.
（発明の構成）
この発明の半導体装置の製造方法は、半導体基板表面に
第１の酸化膜を形成して、この第１の酸化膜上に第１の
窒化＠全形成し、この第１の酸化膜と第１の窒化膜全選
択的に除去して半導体基板表面を露出させ、この露出し
た部分に第１の窒化膜と第１の酸化膜上りなる「ひさし
」をもつアンダカット状の向合形成し、この溝の内面に
第２の酸化膜を形成し、第１の窒化膜と第１の酸化膜２
工び第２の酸化膜の全表面に第２の窒化膜を形成し、「
ひさし」に囲まれた開口部直下の第２の窒化膜全選択的
に除去し、第１の窒化膜と第２の窒化膜をマスクとして
半導体基板を選択的に１１支化するようにしたものであ
る。(Structure of the Invention) A method for manufacturing a semiconductor device of the present invention includes forming a first oxide film on the surface of a semiconductor substrate, completely forming a first nitriding layer on the first oxide film, and The oxide film and the first nitride film are completely selectively removed to expose the semiconductor substrate surface, and an undercut-shaped direction having an "eaves" formed by the first nitride film and the first oxide film is formed on the exposed part. A second oxide film is formed on the inner surface of this groove, and the first nitride film and the first oxide film 2
A second nitride film is formed on the entire surface of the second oxide film.
The second nitride film immediately below the opening surrounded by the "eaves" is completely selectively removed, and the semiconductor substrate is selectively 11 supported using the first nitride film and the second nitride film as masks. It is.
（実施例）
以下、この発明の半導体装置の装造方法の実施例につい
て図面を参照して説明する。第２図１（ａ）〜第２図（
ｇ）はこの発明の第１の実施例を示す図である。(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings. Figure 2 1(a) - Figure 2 (
g) is a diagram showing a first embodiment of the present invention.
まず、第２図（ａ）に示すように、シリコン基板８に第
１゛の熱成長酸化膜９をたとえば２００〜１０００人形
成し、さらにその上に第１の窒化１！ １０ ｋたとえ
ば１０００〜３０００人堆積する。First, as shown in FIG. 2(a), a first thermally grown oxide film 9 of, for example, 200 to 1000 layers is formed on a silicon substrate 8, and then a first nitride film 9 of 1! 10k for example 1000-3000 people deposit.
その後、第２図（ｂ）に示すように第１の窒化膜１０の
分離酸化膜を形成すべき領域にたとえば加熱したリン酸
によるウェットエツチング万代やＣＦ４系カスニよるプ
ラズマエツチング方式にエフ開口１１を設ける。Thereafter, as shown in FIG. 2(b), an F-opening 11 is formed in the region of the first nitride film 10 where the isolation oxide film is to be formed, for example, by wet etching using heated phosphoric acid or plasma etching using CF4-based paint. establish.
続いて第２図（Ｃ）に示すようにこの、開口１１を介し
て、第１の熱成長酸化膜９お工びシリコン基板８をエツ
チングしてたとえは深さ５０００−１０００ＯＡの溝１
２を形成する。Subsequently, as shown in FIG. 2(C), the first thermally grown oxide film 9 is etched through the opening 11 and the silicon substrate 8 is etched to form a groove 1 with a depth of 5000 to 1000 OA, for example.
form 2.
シリコン基板８をエツチングする除、サイ！−”エッチ
を行なわせることに、ｃ９、第１の窒化膜１０お工ひ第
１の熱成長叡化ｇ ｇ 、Ｊ： りなるアンタ”カット
状の「ひさし」１３會形成する。Except for etching the silicon substrate 8! - After etching, the first nitride film 10 is etched to form a first thermally grown etch to form an ant-cut "eaves" 13.
このとき、溝１２の側面は適当なたとえば平行平板型プ
ラズマエツチングにコ？いてＣＦ４＋０２などのエツチ
ングｊｆス全用い適当な力゛ス圧条件を選びエツチング
することにエフ４５°〜６０゛°のチーツヤを設けるこ
とが望ましい。テーノｅは後の選択酸化工程の際、酸化
膜の成長に伴ない第２の窒化膜の逃げる方向を上方に確
保し、活性領域のエツジ部分での応力集中をやわらげ、
結晶欠陥の発生を防止することに効果がある。At this time, the side surfaces of the groove 12 are etched by a suitable parallel plate type plasma etching process, for example. It is preferable to use an etching process such as CF4+02, select appropriate pressure conditions, and provide a cheat of 45° to 60° during etching. During the subsequent selective oxidation process, the TENO-E ensures that the second nitride film escapes upward as the oxide film grows, thereby alleviating stress concentration at the edges of the active region.
It is effective in preventing the occurrence of crystal defects.
その後、第２図（ｄ）に示すように、溝１２（ハ）に第
２の熱成長酸化膜１４をたとえば２００〜１０００人形
成し、ざらに第２の窒化膜１５ｉＬＰ（減圧）ＣＶＤ法
またはプラズマＣＶＤ法を用いてたとえば５００〜２０
０ＯＡ堆積する。Thereafter, as shown in FIG. 2(d), a second thermally grown oxide film 14 is formed in the groove 12(c) by, for example, 200 to 1,000 layers, and then a second nitride film 15i is roughly formed by LP (low pressure) CVD or For example, 500 to 20
Deposit 0OA.
これらのＣＶＤ法は形成膜のステップカパレーノが大変
優れているため、第２図（ｃｉ） ＶＣボす工うに、蒋
１２の内部、特に第１の窒化１夙１０２工ひ第１の熱成
長酸化膜９ニジなる［ひさし」１３の陰になる部分１６
まで完全に第２の窒化膜１５で被うことができる。Since these CVD methods have very good step capabilty of the formed film, it is necessary to remove the inside of the 12, especially the first nitriding layer 102, and the first heat treatment. Portion 16 in the shadow of the growing oxide film 9 [eaves] 13
The second nitride film 15 can completely cover up to 100% of the nitride film.
このとさ、宿性領域上には第１の４１に）俣■０上に第
２の窒化膜１５が油相するため非常に厚い窒化膜が形成
される。At this time, the second nitride film 15 forms an oil phase on the first 41) and 0 (mata) 0 on the host region, so that a very thick nitride film is formed.
しかる後、たとえばｅ Ｆ４−１− Ｈ２ガスを用いた
りアクティブイオンエツチング方法により、第２の窒化
膜１５の異方性エッチングケ行なう。エツチングは第２
の窒化膜１５のエツチングが終了した時点、すなわち第
２図（ｅ）に示す工すに、溝１２の底部１７のみ第２の
熱成長酸化＠】４が露出した時点でストップさせる、
この時点で同じく第２図（Ｃ）に示すように、活性領域
上には、第１の窒化膜１０が残り、また溝１２円の側面
には第２の窒化膜１５が残ることになる。Thereafter, the second nitride film 15 is anisotropically etched using, for example, eF4-1-H2 gas or by active ion etching. Etching is the second
When the etching of the nitride film 15 is completed, that is, when only the bottom 17 of the groove 12 is exposed, the process is stopped when the second thermally grown oxidation layer 4 is exposed. Similarly, as shown in FIG. 2C, the first nitride film 10 remains on the active region, and the second nitride film 15 remains on the side surfaces of the groove 12.
その後、第１の窒化膜１０お工び第２の窒化膜１５全マ
スクとして酸化処理を行ない、第２図（ｆ）に示す工う
なたとえば１μ〜２μの分離用ポ化膜領域１８を得る。Thereafter, the first nitride film 10 and the second nitride film 15 are all subjected to oxidation treatment as a mask to obtain a porous film region 18 for isolation with a thickness of, for example, 1 μm to 2 μm as shown in FIG. 2(f).
酸化膜の成長に伴ない従来の選択酸化法での横方向酸化
に相当する酸化膜が第２の窒化膜１５の下側にテーパ方
向へ成長してゆく。As the oxide film grows, an oxide film corresponding to lateral oxidation in the conventional selective oxidation method grows in the taper direction below the second nitride film 15.
その結果、第２図（ｆ）に示すように、第２の窒化膜１
５は上方へ持ち上げられ、同時に酸化膜断面形状は垂直
に近い形状となる。したがって、本来の活性領域１９に
はバーズビーりのような酸化膜の侵入はなく、捷た第２
の窒化膜１５の逃げる方向が確保されているため、活性
領域１９のエツジ部分での応力集中を和らげることがで
きる。As a result, as shown in FIG. 2(f), the second nitride film 1
5 is lifted upward, and at the same time, the cross-sectional shape of the oxide film becomes nearly vertical. Therefore, there is no invasion of the oxide film like bird's bead into the original active region 19, and the second
Since the direction in which the nitride film 15 escapes is ensured, stress concentration at the edge portions of the active region 19 can be alleviated.
その後、窒化膜をすべて除去し、さらに第１の熱成長酸
化膜９をエツチング除去することにより、第２図（ｇ）
に示すような分離用酸化膜領域１８を得ることができる
。After that, all the nitride film is removed and the first thermally grown oxide film 9 is etched away, as shown in FIG. 2(g).
An isolation oxide film region 18 as shown in FIG. 1 can be obtained.
以上説明したように、第１の実施例では、第１の窒化膜
１０および第１の熱成長酸化膜９．ｃりなる「ひさし」
１３をマスクとして第２の窒化膜１５の異方性エツチン
グを行ない、活性領域１９の上面お工ひテーパを設けた
側面に耐酸化マスクとしての窒化膜を残した状態で分離
用の選択酸化処理を行なう方法である。As explained above, in the first embodiment, the first nitride film 10 and the first thermally grown oxide film 9. c Rinaru “Hisashi”
13 as a mask, the second nitride film 15 is anisotropically etched, and selective oxidation treatment for isolation is performed with the nitride film left as an oxidation-resistant mask on the tapered side surfaces of the upper surface of the active region 19. This is a method of doing this.
したがって、活性領域１９への不要な酸化膜の侵入を防
止することができ、かつ応力集中による結晶欠陥の発生
を防止できるようになる。Therefore, unnecessary invasion of the oxide film into the active region 19 can be prevented, and crystal defects due to stress concentration can be prevented.
また、熱成長シリコンば化物の突出部の発生がないため
、平坦な半導体基板表面が得られる。したがって、多層
配線構造の形成が容易となる利点がある。Further, since no protrusions of thermally grown silicon oxides are generated, a flat semiconductor substrate surface can be obtained. Therefore, there is an advantage that a multilayer wiring structure can be easily formed.
第１の実施例では、第２１（ψに示すように第１の窒化
膜１０とともに「ひさし」１３を形成している第１の熱
成長酸化膜９を残した状態で溝１２円に第２の酸化膜１
４を形成し、さらに全表面に第２の窒化膜１５を堆積し
、しかる後第２の窒化膜１５の異方性エツチングを行な
ったが、この方法によれば「ひさし」１３を形成してい
る第１の熱成長酸化膜９の側面（第２図（ｄ）の２０）
には、第２の窒化膜１５のみ堆積しており、第２の窒化
膜１５の異方性エツチングの際仮にオーバーエッチを行
なった場合、サイドエッチ量にＬつでは、第１の熱成長
酸化膜９の側面が露出し、第１の熱成長酸化膜９の側面
が露出した状態で選択酸化を行なえば、「ひさし」１３
を形成している第１の熱成長酸化膜９中をオキシダント
が拡散し、活性領域１９に酸化膜が成長する可能性があ
る。In the first embodiment, a second thermally grown oxide film 9 is formed in the groove 12 while leaving the first thermally grown oxide film 9 forming the "eaves" 13 together with the first nitride film 10 as shown in the 21st (ψ). oxide film 1
4 was formed, a second nitride film 15 was deposited on the entire surface, and then the second nitride film 15 was anisotropically etched. According to this method, the "eaves" 13 were formed. side surface of the first thermally grown oxide film 9 (20 in FIG. 2(d))
Only the second nitride film 15 is deposited on the surface, and if over-etching is performed during anisotropic etching of the second nitride film 15, if the side etching amount is L, the first thermally grown oxidation layer will be If selective oxidation is performed with the side surfaces of the film 9 exposed and the side surfaces of the first thermally grown oxide film 9 exposed, the "eaves" 13 will be formed.
There is a possibility that the oxidant will diffuse into the first thermally grown oxide film 9 forming the active region 19, and an oxide film will grow in the active region 19.
このような危険全回避する方法として以下に第２の実施
例の説明を行なう。第３図（ａ）〜第３図（ｃ）はこの
発明の第２の実施例を示す図である。A second embodiment will be described below as a method for completely avoiding such risks. FIGS. 3(a) to 3(c) are diagrams showing a second embodiment of the present invention.
この第２の実施例では、第２図（Ｃ）に示す溝１２の形
成工程までは第１の実施例と同様であり説明は省略する
。In this second embodiment, the steps up to the step of forming the groove 12 shown in FIG. 2(C) are the same as those in the first embodiment, and the explanation thereof will be omitted.
この溝１２形成後、第３図（ａ）に示すように、前記［
ひさしＪ１３を形成している第１の熱成長酸化膜９お工
び第１の窒化膜１ｏの複合膜における第１の熱成長酸化
膜９のみをたとえばフッ酸系のエッチャントにより選択
的にエツチング除去する。After forming this groove 12, as shown in FIG.
Selectively remove only the first thermally grown oxide film 9 in the composite film of the first thermally grown oxide film 9 forming the eaves J13 and the first nitride film 1o using, for example, a hydrofluoric acid-based etchant. do.
その後の工程は、第１の実施例と同様であり、溝１２内
に第２の熱成長酸化膜１４を形成し、さらに第３図（ｂ
）に示すように第２の窒化膜１５を減圧ＣＶＤ法または
プラズマＣＶＤ法を用いて堆積する。The subsequent steps are similar to those of the first embodiment, in which a second thermally grown oxide film 14 is formed in the trench 12, and further, as shown in FIG.
), a second nitride film 15 is deposited using a low pressure CVD method or a plasma CVD method.
しかる後、リアクティブイオンエツチング方法により、
第２の窒化膜１５の異方性エツチング全行ない、溝１２
の底部のみ第２の酸化膜１４を露出させる。After that, by reactive ion etching method,
The entire anisotropic etching of the second nitride film 15 is performed, and the groove 12
Only the bottom of the second oxide film 14 is exposed.
さらに、第１の窒化膜１ｏお工び第２の窒化膜１５をマ
スクとして酸化処理全行ない、第３図（Ｃ）に示すよう
な分離用酸化膜領域１８を得る。Further, the first nitride film 1o and the second nitride film 15 are used as a mask to carry out an oxidation process to obtain an isolation oxide film region 18 as shown in FIG. 3(C).
以上説明したように、第２の実施例では、前記「ひさし
」１３の部分はすべて窒化膜で構成されているため、第
２の窒化膜１５の異方性エツチングの際、万一サイドエ
ッチが発生した場合でもこの発明による効果には何ら影
響を及ぼさない。As explained above, in the second embodiment, since the portion of the "eaves" 13 is entirely composed of a nitride film, side etching may occur during anisotropic etching of the second nitride film 15. Even if this occurs, it will not affect the effects of this invention in any way.
（発明の効果）
以上のように、この発明の半導体装置の製造方法によれ
ば、半導体基板上に第１の酸化膜と第１の窒化膜を形成
して選択的に除去して、半導体基板の表面全露出させた
部分に、この第１の酸化膜と第１の窒化膜とに↓る「ひ
さし」を形成するように溝を形成し、この溝内に第２の
酸化膜を形成した後、第１．第２の酸化膜の表面に第２
の窒化膜を形成し、「ひさし」で囲まれた開口部直下の
第２の窒化膜を選択的に除去して、第１．第２の窒化膜
全マスクとして半導体基板を選択的に酸化するようにし
たので、分離用酸化膜領域を形成する選択酸化の際に結
晶欠陥を発生させることなく、バーズビークの形成を防
止できる。(Effects of the Invention) As described above, according to the method of manufacturing a semiconductor device of the present invention, the first oxide film and the first nitride film are formed on the semiconductor substrate and selectively removed. A groove was formed on the entire exposed surface of the first oxide film and the first nitride film to form an "eaves", and a second oxide film was formed within this groove. After, 1st. A second oxide film is formed on the surface of the second oxide film.
A second nitride film is formed immediately below the opening surrounded by the "eaves", and the second nitride film is selectively removed. Since the semiconductor substrate is selectively oxidized using the entire second nitride film mask, the formation of bird's beaks can be prevented without generating crystal defects during selective oxidation to form the isolation oxide film region.
これにともない、従来の選択酸化法の最大の欠点であっ
た寄生領域が形成されないため、最近の微細パターン形
成技術を駆使することにより分離領域の大幅な縮少が可
能となる。したがって、酸化物分離領域を有するＩＣの
高集積度化が可能となる。Along with this, a parasitic region, which was the biggest drawback of the conventional selective oxidation method, is not formed, so that the isolation region can be significantly reduced by making full use of the latest fine pattern forming technology. Therefore, it is possible to increase the degree of integration of an IC having an oxide isolation region.
また、酸化膜による分離構造を有する半導体集積回路装
置全般にわたって応用可能であり、非常に有効なもので
ある。Furthermore, it is applicable to all semiconductor integrated circuit devices having an isolation structure using an oxide film, and is very effective.
第１図（ａ）〜第１図（Ｃ）はそれぞれ従来の選択酸化
法による分離用酸化膜領域の形成方法を工程順に示す断
面図、第２図（ａ）〜第２図（ｇ）はこの発明の半導体
装置の製造方法の一実施例の工程説明図、第３図（ａ）
〜第３図（Ｃ）はこの発明の半導体装置の製造方法の他
の実施例の工程説明図である。
８・・・ンリコン基板、９・・・第１の熱成長酸化膜、
ｌＯ・・・第１の窒化シリコン膜、１２・・・溝、Ｊ３
・・・「ひさし」、１４・・・第２の熱成長酸化膜、１
５・・・第２の窒化シリコン膜、１８・・・分離用酸化
膜、１９・・・活性領域。
特許出願人 沖酸気工業株式会社
手続補正書
昭和５８年１！月１１日
特許庁長官若 杉 オ■ 夫殿
１、事件の表示
昭和５８年 特 許 願第 ７６２００ 号
２、発明の名称
半導体装置の製造方法
３、補正をする者
事件との関係 特 許 出願人（０２９）沖電
気工業株式会社
４、代理人
５、補正命令の日付 昭和 年 月 １１（自
発）６、補正の対象
明細書の発明の詳細な説明の欄および図面７、補正の内
容
別紙の通り
■〕 明細書６頁６行「ことが」を「ことを」と訂正す
る。
２〕 巨１９頁１８行「Ｈ２」を「０２」と訂正する。
３）ｆＵ１０Ｍ５行「第２図（Ｃ） Ｊ ’ｉ ｒ 第
２図（ｅ） Ｊと訂正する。
４）図面第１図および第２図を別紙の通り訂正する。FIGS. 1(a) to 1(C) are cross-sectional views showing a method of forming an isolation oxide film region by a conventional selective oxidation method in the order of steps, and FIGS. 2(a) to 2(g) are FIG. 3(a) is a process explanatory diagram of an embodiment of the method for manufacturing a semiconductor device of the present invention.
- FIG. 3(C) are process explanatory diagrams of another embodiment of the method for manufacturing a semiconductor device of the present invention. 8... Silicon substrate, 9... First thermally grown oxide film,
lO...first silicon nitride film, 12...groove, J3
... "Eaves", 14 ... Second thermally grown oxide film, 1
5... Second silicon nitride film, 18... Isolation oxide film, 19... Active region. Patent Applicant Oki Sanki Kogyo Co., Ltd. Procedural Amendment 1981! May 11th, Mr. Wakasugi Oh, Commissioner of the Japan Patent Office 1. Indication of the case 1982 Patent Application No. 76200 2. Name of the invention Method of manufacturing a semiconductor device 3. Person making the amendment Relationship to the case Patent Applicant (029) Oki Electric Industry Co., Ltd. 4, Agent 5, Date of amendment order: Showa, Month 11 (Voluntary) 6, Detailed description of the invention in the specification subject to amendment and Drawing 7, Contents of amendment as attached. ■] On page 6 of the specification, line 6, ``Koto'' is corrected to ``Koto wo''. 2] On page 19, line 18, "H2" is corrected to "02". 3) Correct line 5 of fU10M as "Figure 2 (C) J 'ir Figure 2 (e) J." 4) Correct Figures 1 and 2 of the drawings as shown in the attached sheet.
Claims (3)
上に第１の窒化膜を形成する工程と、上記第１の窒化膜
および第１の酸化膜を選択的に除去し半導体基板表面を
露出する工程と、上記半導体基板の露出部に上記第１の
窒化膜と前記第１の酸化膜エフなる「ひさし」を持つア
ンダカット状の溝を形成する工程と、この溝の内面に第
２の酸化膜を形成する工程と、上記第１の窒化膜と第１
の酸化膜２工び第２の酸化膜の全表面に第２の窒化膜を
形成する工程と、上記「ひさし」に囲まれた開口部直下
の第２の窒化膜を選択的に除去する工程と、上記第１の
窒化膜お工び第２の窒化膜をマスクとして上記半導体基
板全選択的に酸化する工程とを具備してなる半導体装置
の製造方法。(1) Forming a first oxide film on the surface of the semiconductor substrate and forming a first nitride film thereon, selectively removing the first nitride film and the first oxide film, and removing the first oxide film from the semiconductor substrate. a step of exposing the surface; a step of forming an undercut groove having an "eaves" made of the first nitride film and the first oxide film in the exposed portion of the semiconductor substrate; and forming an undercut groove on the inner surface of the groove. a step of forming a second oxide film; and a step of forming the first nitride film and the first
2 oxide films, a step of forming a second nitride film on the entire surface of the second oxide film, and a step of selectively removing the second nitride film immediately below the opening surrounded by the "eaves". and a step of selectively oxidizing the entire semiconductor substrate using the first nitride film and the second nitride film as a mask.
０°の傾斜金持つことを特徴とする特許請求の範囲第１
項記載の半導体装置の製造方法。(2) The sides of the groove formed in the semiconductor substrate are between 45° and 6°.
Claim 1 characterized by having a slope of 0°.
A method for manufacturing a semiconductor device according to section 1.
する第１の酸化膜および第１の窒化膜の複合膜において
、この第１の酸化膜を選択的に除去する工程を具備して
なることを特徴とする特許請求の範囲第１項記載の半導
体装置の製造方法。(3) A step of selectively removing the first oxide film in the composite film of the first oxide film and the first nitride film constituting the "eaves" after forming the groove in the semiconductor substrate. A method for manufacturing a semiconductor device according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7620083A JPS59202648A (en) | 1983-05-02 | 1983-05-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7620083A JPS59202648A (en) | 1983-05-02 | 1983-05-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59202648A true JPS59202648A (en) | 1984-11-16 |
Family
ID=13598511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7620083A Pending JPS59202648A (en) | 1983-05-02 | 1983-05-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59202648A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61125039A (en) * | 1984-11-21 | 1986-06-12 | Nec Corp | Semiconductor device and manufacture thereof |
| US4863562A (en) * | 1988-02-11 | 1989-09-05 | Sgs-Thomson Microelectronics, Inc. | Method for forming a non-planar structure on the surface of a semiconductor substrate |
| US5068202A (en) * | 1988-12-15 | 1991-11-26 | Sgs-Thomson Microelectronics S.R.L. | Process for excavating trenches with a rounded bottom in a silicon substrate for making trench isolation structures |
| US5182227A (en) * | 1986-04-25 | 1993-01-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56140646A (en) * | 1980-03-10 | 1981-11-04 | Western Electric Co | Method of manufacturing semiconductor circuit on semiconductor silicon substrate |
-
1983
- 1983-05-02 JP JP7620083A patent/JPS59202648A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56140646A (en) * | 1980-03-10 | 1981-11-04 | Western Electric Co | Method of manufacturing semiconductor circuit on semiconductor silicon substrate |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61125039A (en) * | 1984-11-21 | 1986-06-12 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH0478178B2 (en) * | 1984-11-21 | 1992-12-10 | Nippon Electric Co | |
| US5182227A (en) * | 1986-04-25 | 1993-01-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
| US4863562A (en) * | 1988-02-11 | 1989-09-05 | Sgs-Thomson Microelectronics, Inc. | Method for forming a non-planar structure on the surface of a semiconductor substrate |
| US5068202A (en) * | 1988-12-15 | 1991-11-26 | Sgs-Thomson Microelectronics S.R.L. | Process for excavating trenches with a rounded bottom in a silicon substrate for making trench isolation structures |
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