JPS59187897U - Fault indication circuit - Google Patents

Fault indication circuit

Info

Publication number
JPS59187897U
JPS59187897U JP8176483U JP8176483U JPS59187897U JP S59187897 U JPS59187897 U JP S59187897U JP 8176483 U JP8176483 U JP 8176483U JP 8176483 U JP8176483 U JP 8176483U JP S59187897 U JPS59187897 U JP S59187897U
Authority
JP
Japan
Prior art keywords
fault indication
indication circuit
light emitting
voltage
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8176483U
Other languages
Japanese (ja)
Inventor
大槻　光雄
川俣　忠紀
Original Assignee
沖電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 沖電気工業株式会社 filed Critical 沖電気工業株式会社
Priority to JP8176483U priority Critical patent/JPS59187897U/en
Publication of JPS59187897U publication Critical patent/JPS59187897U/en
Pending legal-status Critical Current

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  • Audible And Visible Signals (AREA)
  • Alarm Systems (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の障害、動作表示回路図、第２図は本考案
の一実施例の回路図である。１は系のレベルに対応した
直流電圧、２は基準となる直流電圧、３，４は差動増幅
器、５はバッファ回路、６゜７は障害を表示する発光ダ
イオード、８は分流抵抗を示す。FIG. 1 is a conventional failure and operation display circuit diagram, and FIG. 2 is a circuit diagram of an embodiment of the present invention. 1 is a DC voltage corresponding to the level of the system, 2 is a reference DC voltage, 3 and 4 are differential amplifiers, 5 is a buffer circuit, 6.7 is a light emitting diode that indicates a fault, and 8 is a shunt resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 系の動作監視信号を受容する入力端子１と、該端子１の
電圧を基準電圧２と比較する１対の差動増幅器３，４と
、一方の差動増幅器３の出力に接続される警報用発光ダ
イオード６と、他方の差動増幅器４の出力に接続される
別の警報用発光ダイオード７と、該ダイオード７に並列
に接続され差動増幅器４の残留電圧を吸収する抵抗８と
を有することを特徴とする障害表示回路。An input terminal 1 for receiving a system operation monitoring signal, a pair of differential amplifiers 3 and 4 for comparing the voltage of the terminal 1 with a reference voltage 2, and an alarm terminal connected to the output of one of the differential amplifiers 3. It has a light emitting diode 6, another alarm light emitting diode 7 connected to the output of the other differential amplifier 4, and a resistor 8 connected in parallel to the diode 7 for absorbing the residual voltage of the differential amplifier 4. A fault indication circuit featuring:
JP8176483U 1983-06-01 1983-06-01 Fault indication circuit Pending JPS59187897U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8176483U JPS59187897U (en) 1983-06-01 1983-06-01 Fault indication circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8176483U JPS59187897U (en) 1983-06-01 1983-06-01 Fault indication circuit

Publications (1)

Publication Number Publication Date
JPS59187897U true JPS59187897U (en) 1984-12-13

Family

ID=30211720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8176483U Pending JPS59187897U (en) 1983-06-01 1983-06-01 Fault indication circuit

Country Status (1)

Country Link
JP (1) JPS59187897U (en)

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