JPS59116990U - Level display circuit - Google Patents
Level display circuitInfo
- Publication number
- JPS59116990U JPS59116990U JP955383U JP955383U JPS59116990U JP S59116990 U JPS59116990 U JP S59116990U JP 955383 U JP955383 U JP 955383U JP 955383 U JP955383 U JP 955383U JP S59116990 U JPS59116990 U JP S59116990U
- Authority
- JP
- Japan
- Prior art keywords
- level display
- detection circuit
- display circuit
- light emitting
- emitting diodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のレベル表示回路を示す構成図、第2図は
この考案に係るレベル表示回路の一実施例を示す構成図
、第3図は同じく他の実施例を示す要部の構成図である
。
21・・・主増幅器、22・・・レベル表示回路、R□
〜R□1・・・抵抗、C1〜C4・・・コンデンサ、D
□・・・ダイオード、LED□□〜LED工、・・・発
光ダイオード。Fig. 1 is a block diagram showing a conventional level display circuit, Fig. 2 is a block diagram showing an embodiment of the level display circuit according to this invention, and Fig. 3 is a block diagram of main parts showing another embodiment. It is. 21... Main amplifier, 22... Level display circuit, R□
~R□1...Resistor, C1-C4...Capacitor, D
□...Diode, LED□□~LED work,...Light emitting diode.
Claims (1)
幅検波回路と、この対数増幅検波回路の出力端と基準電
位点との間に直列に接続される複数の発光ダイオードと
、これら複数の発光ダイオードの対応する各一端と前記
対数増幅検波回路の出力端との間に接続される複数のバ
イアス用抵抗とを具備してなることを特徴とするレベル
表示同A logarithmic amplification and detection circuit that logarithmically amplifies and detects a signal for level display, a plurality of light emitting diodes connected in series between the output terminal of this logarithm amplification and detection circuit and a reference potential point, and these plurality of light emitting diodes. A level display system characterized by comprising a plurality of bias resistors connected between each corresponding end of the diode and the output end of the logarithmic amplification detection circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP955383U JPS59116990U (en) | 1983-01-26 | 1983-01-26 | Level display circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP955383U JPS59116990U (en) | 1983-01-26 | 1983-01-26 | Level display circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59116990U true JPS59116990U (en) | 1984-08-07 |
Family
ID=30141010
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP955383U Pending JPS59116990U (en) | 1983-01-26 | 1983-01-26 | Level display circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59116990U (en) |
-
1983
- 1983-01-26 JP JP955383U patent/JPS59116990U/en active Pending
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