JPS6051472U - Level meter circuit - Google Patents

Level meter circuit

Info

Publication number
JPS6051472U
JPS6051472U JP14232783U JP14232783U JPS6051472U JP S6051472 U JPS6051472 U JP S6051472U JP 14232783 U JP14232783 U JP 14232783U JP 14232783 U JP14232783 U JP 14232783U JP S6051472 U JPS6051472 U JP S6051472U
Authority
JP
Japan
Prior art keywords
level meter
circuit
meter circuit
logarithmic compression
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14232783U
Other languages
Japanese (ja)
Inventor
芳樹 古田
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP14232783U priority Critical patent/JPS6051472U/en
Publication of JPS6051472U publication Critical patent/JPS6051472U/en
Pending legal-status Critical Current

Links

Landscapes

  • Measuring Instrument Details And Bridges, And Automatic Balancing Devices (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のレベルメータ回路の構成を示すブロック
図、第2図は第1図のレベルメータ回路の入出力特性を
示す図、第3図は本考案の一実施例の構成を示すブロッ
ク図、第4図は本考案の一実施例における作用の説明に
供する入出力特性図、第5図はレベルメータの一例を示
す正面図、第6図は本考案の他の実施例の構成を示すブ
ロック図、第7図は本考案の他の実施例における作用の
説明に供する入出力特性図である。
Figure 1 is a block diagram showing the configuration of a conventional level meter circuit, Figure 2 is a diagram showing the input/output characteristics of the level meter circuit in Figure 1, and Figure 3 is a block diagram showing the configuration of an embodiment of the present invention. 4 is an input/output characteristic diagram for explaining the operation of one embodiment of the present invention, FIG. 5 is a front view showing an example of a level meter, and FIG. 6 is a diagram showing the configuration of another embodiment of the present invention. The block diagram shown in FIG. 7 is an input/output characteristic diagram for explaining the operation of another embodiment of the present invention.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 被測定電圧を対数圧縮回路を介してレベルメータで表示
するレベルメータ回路において、レベルメータの入力電
圧が所定値を越えたことを検出する検出手段を備え、対
数圧縮回路の圧縮特性を切換可能に構成し、前記検出手
段の出力により対数圧縮特性を切換えることを特徴とす
るレベルメータ回路。
In a level meter circuit that displays the voltage to be measured with a level meter via a logarithmic compression circuit, it is equipped with a detection means that detects when the input voltage of the level meter exceeds a predetermined value, making it possible to switch the compression characteristics of the logarithmic compression circuit. 1. A level meter circuit comprising: a level meter circuit configured to switch logarithmic compression characteristics according to an output of said detection means;
JP14232783U 1983-09-16 1983-09-16 Level meter circuit Pending JPS6051472U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14232783U JPS6051472U (en) 1983-09-16 1983-09-16 Level meter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14232783U JPS6051472U (en) 1983-09-16 1983-09-16 Level meter circuit

Publications (1)

Publication Number Publication Date
JPS6051472U true JPS6051472U (en) 1985-04-11

Family

ID=30318058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14232783U Pending JPS6051472U (en) 1983-09-16 1983-09-16 Level meter circuit

Country Status (1)

Country Link
JP (1) JPS6051472U (en)

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