JPS58182238A - Electronic parts - Google Patents

Electronic parts

Info

Publication number
JPS58182238A
JPS58182238A JP57066154A JP6615482A JPS58182238A JP S58182238 A JPS58182238 A JP S58182238A JP 57066154 A JP57066154 A JP 57066154A JP 6615482 A JP6615482 A JP 6615482A JP S58182238 A JPS58182238 A JP S58182238A
Authority
JP
Japan
Prior art keywords
lead frame
plating
junction
resin
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57066154A
Other languages
Japanese (ja)
Inventor
Yukihiro Inoue
幸弘 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP57066154A priority Critical patent/JPS58182238A/en
Publication of JPS58182238A publication Critical patent/JPS58182238A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To realize cost down through sealing by resin after changing Au plating to Sn plating by flip chip junction of an LSI chip on a lead frame. CONSTITUTION:Resist masks 10, 11 are selectively formed in both sides of metal plate 9 and these are etched, thereby forming a lead frame 5 where only the junction area is made thinner. A lead frame 5 is fixed to a supporting means, an LSI chip 6 is directly fixed by the flip chip junction method and it is sealed by resin 9. In such a structure, Au plating is unnecessary and the Sn plating is enough for the solder bump and accordingly cost reduction can be realized. In addition, area required for junction is reduced also realizing reduction in size.

Description

【発明の詳細な説明】 本発明は、金属板を打ち抜いたり、エツチングしたりし
て作ったリードフレーム上にＬＳＩチップをボンディン
グし、その後、樹脂でモールドする構成とした電子部品
の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in electronic components in which an LSI chip is bonded onto a lead frame made by punching or etching a metal plate, and then molded with resin. be.

第１図に従来の電子部品の構成を示す。FIG. 1 shows the configuration of a conventional electronic component.

図に於て、／はリードフレーム、２はＬＳＩチップ、３
はワイヤー、りは樹脂である。In the figure, / is a lead frame, 2 is an LSI chip, and 3 is a lead frame.
is wire and ri is resin.

′　図に示すように、従来は、ＬＳＩチップをワイヤー
ボンディングする構成であった。しかし、この構成には
、ワイヤーボンディング用としてＡｕメッキを施す必要
があり高価になるという欠点があった。' As shown in the figure, conventionally, LSI chips were wire-bonded. However, this configuration has the disadvantage that it is expensive because it requires Au plating for wire bonding.

本発明は上記欠点を除去することを目的としてなされた
ものであり、リードフレーム上にＬＳＩチップをフリッ
プチップボンディングするという全く新規な構成を採用
することにより上記Ａｕメッキを不要として（フリップ
チップボンディング〔半田バンプ〕の場合は、Ｓｎメッ
キで充分）コストダウンをはかった電子部品を提供する
ものである。The present invention has been made with the aim of eliminating the above-mentioned drawbacks, and eliminates the need for the above-mentioned Au plating by adopting a completely new configuration in which an LSI chip is flip-chip bonded onto a lead frame (flip-chip bonding). In the case of solder bumps, Sn plating is sufficient) This provides electronic components with reduced costs.

ＸＪ−７図に本発明の一実施例の構成を示す。Figure XJ-7 shows the configuration of an embodiment of the present invention.

図に於て、ｊはリードフレーム、乙はＬＳＩｆ−ツブ、
Ｚはフリップチップ用バンプ、♂は樹脂である。In the figure, j is the lead frame, O is the LSIf-tube,
Z is a bump for flip chip, and ♂ is resin.

図に示すように、ＬＳＩチップをフリップチップボンデ
ィングする構成としている。すなわち、ボンディングの
方法は、フリップチップ方式にてダイレクトボンディン
グする。この際、リードフレームの中心（ボンディング
部分）が変形しないように、支持台の上でリードフレー
ムを固定シ、ボンディングすることが必要である。ボン
ディングした後は、従来のものと同様に樹脂でモールド
し、外部に突出しているリードをフレーミングする。As shown in the figure, the LSI chip is configured to be flip-chip bonded. That is, the bonding method is direct bonding using a flip chip method. At this time, it is necessary to fix and bond the lead frame on a support stand so that the center (bonding part) of the lead frame does not deform. After bonding, it is molded with resin in the same way as conventional products, and the leads protruding to the outside are framed.

リードフレームｊは、第３図に示すように、ボンディン
グ部分のみを薄くし、他の部分は厚くした構４成として
いる。このような構成とすることにより、ボンディング
部分に於てファインパターンが得られると共に他の部分
の強度も充分なものとなる。As shown in FIG. 3, the lead frame j has a structure 4 in which only the bonding portion is thin and the other portions are thick. By adopting such a structure, a fine pattern can be obtained in the bonding part, and the strength of other parts can also be made sufficient.

ボンディング部分のみが他の部分より薄しリードフレー
ムを得る方法としては、第７図に示すように、金属板２
の片側にハーフエツチング用のレジスト／θをコートし
、反対側にファイン・パターン用のレジスト／／をコー
トしてエツチングする方法がある。（ａ）　−（ｂ）　
−（Ｃ）の順にエツチングされていき、最終的に、（ｄ
）に示すような、ボンディング部分のみが薄い構造のリ
ードフレームＳを得ることができる。To obtain a lead frame in which only the bonding part is thinner than other parts, as shown in FIG.
There is a method in which one side of the pattern is coated with a half-etching resist /θ and the other side is coated with a fine pattern resist. (a) - (b)
-(C), and finally, (d
), it is possible to obtain a lead frame S having a structure in which only the bonding portion is thin.

以上詳細に説明したよう′に、本発明の電子部品は、金
属板を打ち抜いたり、エツチングしたりして作ったリー
ドフレーム上にＬＳＩチップをフリップチップボンディ
ングし、その後、樹脂でモールドする構成としたことを
特徴とするものであり、本発明によれば、従来のような
Ａｕメッキを必要とせずコストダウンをはかることがで
きると共に、ボンディングに要する面積が小さくてすむ
ので小型部品の作成が可能となるという効果を奏するも
のである。As explained above in detail, the electronic component of the present invention has a structure in which an LSI chip is flip-chip bonded onto a lead frame made by punching or etching a metal plate, and then molded with resin. According to the present invention, it is possible to reduce costs by not requiring conventional Au plating, and the area required for bonding is small, making it possible to create small parts. This has the effect of becoming.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（１）及び（２）は断面図、第１図（３）は平面
図、第一図（１）及び（２）は断面図、第一図（３）は
平面図、第３図は断面図、第７図は製造工程図である。 符号の説明 、５：リードフレーム、乙：ＬＳＩチップ、７：７リツ
プチツプ用バンプ、♂：樹脂、？＝金属板、１０．／／
ニレジスト。 代理人　弁理士　　福　士　愛　彦（他２名）（２）　
　　　　　　　　　　　第２図第μ図　　　　５Figures 1 (1) and (2) are sectional views, Figure 1 (3) is a plan view, Figure 1 (1) and (2) are sectional views, Figure 1 (3) is a plan view, and Figure 1 (3) is a plan view. The figure is a sectional view, and FIG. 7 is a manufacturing process diagram. Explanation of symbols, 5: Lead frame, O: LSI chip, 7: 7 lip chip bump, ♂: Resin, ? = metal plate, 10. ///
Ni resist. Agent Patent attorney Aihiko Fukushi (and 2 others) (2)
Figure 2 Figure μ Figure 5

Claims (1)

【特許請求の範囲】[Claims] ｌ　金属板を打ち抜いたり、エツチングしたりして作っ
タリードフレーム上にＬＳＩチップをフリップチップボ
ンディングし、その後、樹脂でモールドする構成とした
ことを特徴とする電子部品。l An electronic component characterized in that an LSI chip is flip-chip bonded onto a tally lead frame made by punching or etching a metal plate, and then molded with resin.
JP57066154A 1982-04-19 1982-04-19 Electronic parts Pending JPS58182238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57066154A JPS58182238A (en) 1982-04-19 1982-04-19 Electronic parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57066154A JPS58182238A (en) 1982-04-19 1982-04-19 Electronic parts

Publications (1)

Publication Number Publication Date
JPS58182238A true JPS58182238A (en) 1983-10-25

Family

ID=13307658

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57066154A Pending JPS58182238A (en) 1982-04-19 1982-04-19 Electronic parts

Country Status (1)

Country Link
JP (1) JPS58182238A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0771519A4 (en) * 1994-07-19 1998-02-25 Olin Corp Integrally bumped electronic package components
JP2010192857A (en) * 2009-02-20 2010-09-02 Sumitomo Metal Mining Co Ltd Leadframe and method of manufacturing the same
US8835788B2 (en) 2010-08-23 2014-09-16 Mitsumi Electric Co., Ltd. Slide switch

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50143468A (en) * 1974-05-08 1975-11-18

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50143468A (en) * 1974-05-08 1975-11-18

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0771519A4 (en) * 1994-07-19 1998-02-25 Olin Corp Integrally bumped electronic package components
JP2010192857A (en) * 2009-02-20 2010-09-02 Sumitomo Metal Mining Co Ltd Leadframe and method of manufacturing the same
US8835788B2 (en) 2010-08-23 2014-09-16 Mitsumi Electric Co., Ltd. Slide switch

Similar Documents

Publication Publication Date Title
US7622332B2 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6777265B2 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7307347B2 (en) Resin-encapsulated package, lead member for the same and method of fabricating the lead member
WO2003103038A1 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JPS58182238A (en) Electronic parts
JPH11260990A (en) Lead frame, resin-sealed semiconductor device and its manufacture
JPS6086851A (en) Resin sealed type semiconductor device
JP2001298102A (en) Packaging structure of functional element and its manufacturing method
JP3670371B2 (en) Semiconductor device and manufacturing method thereof
JPH01187841A (en) Semiconductor device
JP3358114B2 (en) Semiconductor device and manufacturing method thereof
JP2003188332A (en) Semiconductor device and its manufacturing method
JPH11260950A (en) Semiconductor device and manufacture thereof
JP2003007904A (en) Semiconductor device
JPH04322435A (en) Semiconductor device and manufacture thereof
JPH04318959A (en) Semiconductor device
JPH05211268A (en) Semiconductor device
JPS5897849A (en) Semiconductor element
JPH11288978A (en) Semiconductor device
JPH05144816A (en) Face-down bonding method
JPH10214934A (en) Semiconductor device and its manufacture
JPH0378235A (en) Lead frame
JPH07147292A (en) Manufacture of semiconductor device
JPH0294463A (en) Semiconductor device
JPS59202643A (en) Connecting method of large scale integration