JPH0287538A - Tape carrier module - Google Patents
Tape carrier moduleInfo
- Publication number
- JPH0287538A JPH0287538A JP63238708A JP23870888A JPH0287538A JP H0287538 A JPH0287538 A JP H0287538A JP 63238708 A JP63238708 A JP 63238708A JP 23870888 A JP23870888 A JP 23870888A JP H0287538 A JPH0287538 A JP H0287538A
- Authority
- JP
- Japan
- Prior art keywords
- copper foil
- film
- bonding
- inner lead
- outer lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 229910000881 Cu alloy Inorganic materials 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 claims 1
- 239000010949 copper Substances 0.000 claims 1
- 238000005476 soldering Methods 0.000 claims 1
- 239000011889 copper foil Substances 0.000 abstract description 14
- 229910000679 solder Inorganic materials 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 12
- 238000007747 plating Methods 0.000 abstract description 9
- 229910020816 Sn Pb Inorganic materials 0.000 abstract description 4
- 229910020922 Sn-Pb Inorganic materials 0.000 abstract description 4
- 229910008783 Sn—Pb Inorganic materials 0.000 abstract description 4
- 229910015363 Au—Sn Inorganic materials 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 239000009719 polyimide resin Substances 0.000 abstract description 2
- 238000009713 electroplating Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はテープキャリアモジュール及びテープキャリア
モジュールの製造方法係り、特にアウタリード部への金
属膜形成に好適なものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a tape carrier module and a method for manufacturing the tape carrier module, and is particularly suitable for forming a metal film on an outer lead portion.
従来のテープキャリアモジュールは、特開昭５７１４９
７５９号公報に記載のように、半導体チップをボンディ
ングする前にインナリード部及びアウタリート部に５ｎ
−Ｐｂ系はんだめっき処理を施こしている。The conventional tape carrier module is disclosed in Japanese Patent Application Laid-Open No. 57149.
As described in Japanese Patent No. 759, 5n is applied to the inner lead part and outer lead part before bonding the semiconductor chip.
-Pb-based solder plating treatment is applied.
ところが上記従来技術ではインナリードボンディング部
とアウタリードボンディング部のはんだ層厚さが同じに
なっており、インナリードボンディングに最適なはんだ
層厚さにすると、アウタボンディング部のはんだ量が不
足してしまい良好な接続が出来ない。また逆にアウタリ
ードボンディング部に最適なはんだ層厚さでは、インナ
リードボンディング部のはんだ量が過多になって、はん
だブリッジ及びはんだ流れ出しによる回路ショート等の
不良が発生するという欠点がある。However, in the above-mentioned conventional technology, the solder layer thickness of the inner lead bonding part and the outer lead bonding part is the same, and when the solder layer thickness is set to the optimum thickness for inner lead bonding, the amount of solder in the outer bonding part is insufficient. I can't make a good connection. On the other hand, if the solder layer thickness is optimal for the outer lead bonding part, the amount of solder in the inner lead bonding part becomes excessive, resulting in defects such as circuit shorts due to solder bridging and solder flowing out.
本発明の目的は、上記のインナリードボンディング部と
アウタリードボンディング部のめっき皮膜形成法を改良
することによって上記従来技術の問題点を無くすること
にある。An object of the present invention is to eliminate the problems of the prior art by improving the method of forming the plating film on the inner lead bonding portion and the outer lead bonding portion.
すなわち本発明では、インナリードボンディングに最適
な皮膜処理を行なった状態で半導体チップのボンディン
グを行ない、この後でアウタリードに最適な皮膜処理を
行なうようにしたものである。That is, in the present invention, bonding of the semiconductor chip is performed in a state in which a film treatment optimal for inner lead bonding has been performed, and thereafter, a film treatment optimal for outer leads is performed.
この方法によれば、インナリードボンディング前のテー
プキャリアはインナリードボンディングに最も適した金
属及び皮膜厚さを選定でき、その後のアウタリードボン
ディングに対しては、インナリードボンディング部への
ボンディング性を気にせずアウタリードボンディングに
最適な金属及び皮膜厚さを選定出来る。According to this method, the metal and coating thickness most suitable for inner lead bonding can be selected for the tape carrier before inner lead bonding, and for the subsequent outer lead bonding, the bondability to the inner lead bonding part must be taken into consideration. You can select the optimal metal and film thickness for outer lead bonding without having to worry about
以下、本発明の一実施例を第１図により説明する。 An embodiment of the present invention will be described below with reference to FIG.
第１図は本発明になるテープキャリアモジュールの主要
製造工程を示す断面図である。（ａ）〜（ｄ）において
、絶縁テープ１上には銅箔が貼り付けられパターニング
されて銅箔パターン２が形成される。絶縁テープ１の一
部を取り除いた個所にインナリード３及びアラタリー１
〜４を形成する。FIG. 1 is a sectional view showing the main manufacturing process of the tape carrier module according to the present invention. In (a) to (d), a copper foil is pasted on the insulating tape 1 and patterned to form a copper foil pattern 2. Inner lead 3 and inner lead 1 are attached to the area where part of the insulating tape 1 is removed.
- form 4.
銅箔パターン２上にはＳｎ膜５が形成されており、イン
ナリード３にはバンプ６を有する半導体チップ７が形成
されている。Ｓｎｎ膜上上びインナリード部のバンプ６
上にははんだ皮膜８が形成される。A Sn film 5 is formed on the copper foil pattern 2, and a semiconductor chip 7 having bumps 6 is formed on the inner lead 3. Bump 6 on the top of the Snn film and on the inner lead part
A solder film 8 is formed thereon.
以上の構成においてテープキャリアモジュールの構成及
び製造方法を説明する。第１図（ａ）において、ポリイ
ミド樹脂よりなる絶縁テープ１の一部を取り除いた一面
に銅箔２を貼り付ける。次いで、銅箔２上に必要パター
ンの焼付、現象処理を用いたホト処理工程を通し不要銅
箔を二ノチング処理にて除去し必要銅箔パターン２を得
る。次にパターニングされたテープを無電解Ｓｎめっき
処理工程を通して、（ｂ）に示す如く、銅箔パターン上
にＳｎめっき皮膜５を形成する。このＳｎ皮膜５は（Ｃ
）図においてチップ７上のＡｕめっきで形成されたバン
プ６とＡ ｕ −Ｓ ｎ接合を行なうに最も適した厚さ
付着させる。Ｓｎ皮膜５を形成したインナリード３とＡ
ｕバンプ６を有するチップ７は、位置合わせ整合された
後、インナリードボンダ（図示なし）によって圧力と温
度を付加し、Ａｕ−Ｓｎ接合を行なう （（Ｃ）図）。With the above configuration, the configuration and manufacturing method of the tape carrier module will be explained. In FIG. 1(a), a copper foil 2 is pasted on one side of an insulating tape 1 made of polyimide resin from which a portion has been removed. Next, a necessary pattern is printed on the copper foil 2, a photo-processing process using a phenomenon process is performed, and unnecessary copper foil is removed by a double notching process to obtain a necessary copper foil pattern 2. Next, the patterned tape is subjected to an electroless Sn plating process to form a Sn plating film 5 on the copper foil pattern, as shown in (b). This Sn film 5 is (C
) In the figure, the most suitable thickness for forming an Au-Sn bond with the bump 6 formed by Au plating on the chip 7 is deposited. Inner lead 3 and A on which Sn film 5 was formed
After the chip 7 having the U-bumps 6 is aligned and aligned, pressure and temperature are applied by an inner lead bonder (not shown) to perform Au-Sn bonding (Figure (C)).
次いでチップボンディングされたテープを電解５ｎ−ｐ
ｂめっき処理工程を通すことにより、（ｄ）図に示す如
く金属露出部にアウタリードに適した厚さのＳ ｎ −
Ｐ ｂはんだめっき皮膜８を形成する。Then, the chip-bonded tape was electrolytically 5n-p
By passing through the plating process (b), S n − of a thickness suitable for the outer lead is formed on the exposed metal portion as shown in figure (d).
A Pb solder plating film 8 is formed.
以上述へた如く本発明によれば、インナリード部とアウ
タリード部それぞれに適した組成及び厚さの皮膜を形成
することが出来、インナリードボンディング及びアウタ
リードボンディングのボンディング歩留りを大巾に向上
させることが可能である。As described above, according to the present invention, it is possible to form a film having a composition and thickness suitable for each of the inner lead part and the outer lead part, and the bonding yield of inner lead bonding and outer lead bonding is greatly improved. Is possible.
なお、本実施例ではインナリードボンディング前の第１
層皮膜にＳｎ皮膜を用いたが、Ａｕ皮膜及びＳｎ Ｐ
ｂ皮膜を用いることも出来る。また、インナリートボン
ディング後の第２層皮膜にＳｎ−Ｐ ｂ系はんだを用い
たが、Ｓｎ皮膜、Ｓｎ −Ｐｂ皮膜、Ａｕ皮膜、Ａｕ−
Ｎｉ皮膜も同様に用いることができる。Note that in this example, the first
Although a Sn film was used as the layer film, Au film and SnP
b film can also be used. In addition, although Sn-Pb solder was used for the second layer film after internal bonding, Sn film, Sn-Pb film, Au film, Au-
Ni films can be used as well.
第１図は本発明の一実施例のテープキャリアモジュール
の構成及び製造方法を示す断面図である。
１・・・絶縁テープ、２・・銅箔パターン、３・・イン
ナリート、４・・アウタリード、５・・Ｓｎ皮膜、７・
・・半導体チップ、８・・・はんだ皮膜。FIG. 1 is a sectional view showing the structure and manufacturing method of a tape carrier module according to an embodiment of the present invention. 1... Insulating tape, 2... Copper foil pattern, 3... Inner lead, 4... Outer lead, 5... Sn film, 7...
...Semiconductor chip, 8...Solder film.
Claims (1)
ンを有するテープキャリアに半導体素子をインナリード
ボンディングし、アウタリードボンディングをはんだ接
続で行なうテープキャリアモジュールにおいて、パター
ニングされたインナリード及びアウタリードに第１の金
属膜を形成し、次いで半導体チップを前記インナリード
にボンディングした後、露出したアウタリード部に第２
の金属膜を形成したことを特徴とするテープキャリアモ
ジュール。1. In a tape carrier module in which inner leads are bonded to a tape carrier having a pattern made of copper or copper alloy on an insulating film, and outer leads are bonded by soldering, a patterned inner lead and an outer lead are bonded to each other. After forming a first metal film and bonding a semiconductor chip to the inner leads, a second metal film is formed on the exposed outer leads.
A tape carrier module characterized by forming a metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63238708A JPH0287538A (en) | 1988-09-26 | 1988-09-26 | Tape carrier module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63238708A JPH0287538A (en) | 1988-09-26 | 1988-09-26 | Tape carrier module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0287538A true JPH0287538A (en) | 1990-03-28 |
Family
ID=17034097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63238708A Pending JPH0287538A (en) | 1988-09-26 | 1988-09-26 | Tape carrier module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0287538A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0437149A (en) * | 1990-06-01 | 1992-02-07 | Toshiba Corp | Semiconductor device and manufacture of the same |
-
1988
- 1988-09-26 JP JP63238708A patent/JPH0287538A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0437149A (en) * | 1990-06-01 | 1992-02-07 | Toshiba Corp | Semiconductor device and manufacture of the same |
| US5654584A (en) * | 1990-06-01 | 1997-08-05 | Kabushiki Kaisha Toshiba | Semiconductor device having tape automated bonding leads |
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