JPS5899915U

JPS5899915U - gain control circuit

Info

Publication number: JPS5899915U
Application number: JP19818681U
Authority: JP
Inventors: 嶋野　収
Original assignee: 株式会社東芝
Priority date: 1981-12-25
Filing date: 1981-12-25
Publication date: 1983-07-07

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の利得制御回路の一例を示す回路図、第２
図は同じく他の例を示す回路図、第３図、はこの考案に
係る利得制御回路の一実施例を示す回路図である。Ｑ２□〜Ｑ３ｏ・・・・・・トランジスタ、Ｒ２１〜Ｒ
２４・・・・・・抵抗、２１．２２・・・・・・入力端
子、２４．２５・・・・・・端子、２６・・・・・・利
得制御信号発生回路、２７．　３０゜３１・・・・・・
定電流回路、２８．２９・・・・・・出力端子。Figure 1 is a circuit diagram showing an example of a conventional gain control circuit;
FIG. 3 is a circuit diagram showing another example, and FIG. 3 is a circuit diagram showing an embodiment of the gain control circuit according to the invention. Q2□~Q3o...Transistor, R21~R
24...Resistor, 21.22...Input terminal, 24.25...Terminal, 26...Gain control signal generation circuit, 27. 30゜31・・・・・・
Constant current circuit, 28.29... Output terminal.

Claims

【実用新案登録請求の範囲】[Scope of utility model registration request]

ベースにそれぞれ相補的な入力信号が供給される第１、
第２のトランジスタと、この第１、第２のトランジスタ
のコレクターエミッタ電流路にそれぞれベースが接続さ
れる第３、第４−の叶うンジスタを有し差動増幅器構成
とされる負荷回路と、入出力端子のうちのいずれか一方
の端子が交流的に基準電位側に接続され他方の端子がそ
れぞれ前記第１、第２のトランジスタのコレクタ・エミ
ッタ電流路と前記第３、第４のトランジスタのベースと
の接続点に接続される第１、第２の定電圧回路と、利得
制御信号のレベルに応じて前記第１、第２の定電圧回路
を流れる直流電流レベルを制御する制御回路とを具備し
た利得制御回路。a first, each of which is supplied with a complementary input signal to the base;
a load circuit having a differential amplifier configuration, including a second transistor, and third and fourth transistors whose bases are connected to collector-emitter current paths of the first and second transistors, respectively; One of the output terminals is connected to the AC reference potential side, and the other terminal is connected to the collector-emitter current paths of the first and second transistors and the bases of the third and fourth transistors, respectively. and a control circuit that controls the level of direct current flowing through the first and second constant voltage circuits according to the level of the gain control signal. gain control circuit.