JPS582018U - power circuit - Google Patents
power circuitInfo
- Publication number
- JPS582018U JPS582018U JP9397381U JP9397381U JPS582018U JP S582018 U JPS582018 U JP S582018U JP 9397381 U JP9397381 U JP 9397381U JP 9397381 U JP9397381 U JP 9397381U JP S582018 U JPS582018 U JP S582018U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- emitter
- base
- collector
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の電源回路を示す回路図、第２図はこの考
案の一実施例を示す回路図である。
１１．１２・・・・・・整流回路、１５．１６・・曲負
荷回路、Ｔ、１〜Ｔｒ７・・・・・・トランジスタ、Ｒ
１〜Ｒ１ｏ・・・・・・抵抗。FIG. 1 is a circuit diagram showing a conventional power supply circuit, and FIG. 2 is a circuit diagram showing an embodiment of this invention. 11.12... Rectifier circuit, 15.16... Curved load circuit, T, 1 to Tr7... Transistor, R
1~R1o...Resistance.
Claims (1)
と、第１の整流回路の出力端と第１の負荷回路間にエミ
ッタ・コレクタ路が接続された第１の制御トランジスタ
と、この第１の制御トランジスタの出力電圧を分圧して
取出すための抵抗分圧回路と、前記第１の制御トランジ
スタのベースにコレクタが接続され、前記分圧回路にベ
ースが接続され、エミッタが基準電圧源に接続された第
１の誤差増幅トランジスタと、この第１の誤差増幅トラ
ンジスタのエミッタに抵抗を介してコレクタが接続され
た第３のトランジスタと、前記第２の整流回路の出力端
と第２の負荷回路間にエミッタ・コレクタ路が接続され
た第２の制御トランジスタと、この第２の制御トランジ
スタの出力電圧を分圧して取出すための抵抗分圧回路と
、前記第２の制御トランジスタのベースにコレクタが接
続され、前記分圧回路にベースが接続され、エミッタが
基準電圧源に接続された第２の誤差増幅トランジスタと
、この第２の誤差増幅トランジスタのエミッタに抵抗を
介してコレクタが接続された第 −６のトランジスタ
と、前記第６のトランジスタのベース、および第３のト
ランジスタのエミッタを接地電位に接続し、該第３のト
ランジスタのベーースと第６のトランジスタのエミッタ
にコレクタ出力を供給し、ベースには制御信号が加えら
れ、前記第３、第６のトランジスタをオン・オフ制御す
る第７のトランジスタとを具備したことを特徴とする電
源回路。first and second rectifier circuits that obtain positive and negative rectifier outputs, respectively; a first control transistor with an emitter-collector path connected between the output terminal of the first rectifier circuit and a first load circuit; A resistive voltage divider circuit for dividing and extracting the output voltage of the first control transistor, a collector connected to the base of the first control transistor, a base connected to the voltage divider circuit, and an emitter connected to a reference voltage. a first error amplification transistor connected to the source; a third transistor whose collector is connected to the emitter of the first error amplification transistor via a resistor; a second control transistor with an emitter-collector path connected between the load circuits; a resistive voltage divider circuit for dividing and extracting the output voltage of the second control transistor; and a base of the second control transistor. a second error amplification transistor having a collector connected to the voltage divider circuit, a base connected to the voltage dividing circuit, and an emitter connected to a reference voltage source; and a collector connected to the emitter of the second error amplification transistor via a resistor. A -6th transistor, a base of the sixth transistor, and an emitter of the third transistor are connected to a ground potential, and a collector output is supplied to the base of the third transistor and the emitter of the sixth transistor. and a seventh transistor to which a control signal is applied to the base to control on/off of the third and sixth transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9397381U JPS582018U (en) | 1981-06-25 | 1981-06-25 | power circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9397381U JPS582018U (en) | 1981-06-25 | 1981-06-25 | power circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS582018U true JPS582018U (en) | 1983-01-07 |
Family
ID=29888925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9397381U Pending JPS582018U (en) | 1981-06-25 | 1981-06-25 | power circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS582018U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60151728A (en) * | 1984-01-19 | 1985-08-09 | Sharp Corp | Power supply on/off control circuit |
| WO2007080828A1 (en) * | 2006-01-10 | 2007-07-19 | Rohm Co., Ltd. | Negative output regulator circuit and electric device using same |
-
1981
- 1981-06-25 JP JP9397381U patent/JPS582018U/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60151728A (en) * | 1984-01-19 | 1985-08-09 | Sharp Corp | Power supply on/off control circuit |
| WO2007080828A1 (en) * | 2006-01-10 | 2007-07-19 | Rohm Co., Ltd. | Negative output regulator circuit and electric device using same |
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