JPS5896763A - Cmos semiconductor device - Google Patents

Cmos semiconductor device

Info

Publication number
JPS5896763A
JPS5896763A JP56194974A JP19497481A JPS5896763A JP S5896763 A JPS5896763 A JP S5896763A JP 56194974 A JP56194974 A JP 56194974A JP 19497481 A JP19497481 A JP 19497481A JP S5896763 A JPS5896763 A JP S5896763A
Authority
JP
Japan
Prior art keywords
channel
gate
ions
annealing
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56194974A
Other languages
Japanese (ja)
Other versions
JPH0221148B2 (en
Inventor
Juri Kato
樹理 加藤
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP56194974A priority Critical patent/JPS5896763A/en
Publication of JPS5896763A publication Critical patent/JPS5896763A/en
Publication of JPH0221148B2 publication Critical patent/JPH0221148B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain the CMOS device having gate channel lengths of 2mum or less by a method wherein the device is activated larger than the case when annealing and diffusion are performed in N2 gas as usual by adopting annealing according to ramp heating, and moreover the P type channel and the N type channel are made as controllable together to make junction depths shallow. CONSTITUTION:Wells are provided as usual in an Si substrate, Poly-Si gate electrode are provided on field oxide films and gate oxide films, B ions and P ions having concentration of 4X10<15>cm<-2> respectively are implanted to each at energy of 40KeV to form drain layers and source layers, and the P channel and the N channel FET's are formed. After then, ramp heating is performed for about 6sec at the surface heater temperature of 1,300 deg.C to anneal. Accordingly junction depths of the implanted layers of B ions and P ions are made as controllable to the grade of about 0.4mum, and the CMOS device having gate lengths of 2mum or less at the P channel and the N channel together can be formed having favorable controllability.

Description

【発明の詳細な説明】 本発明は、０Ｍ０Ｅ！半導体装置に関する。[Detailed description of the invention] The present invention is 0M0E! Related to semiconductor devices.

従来０ＭＯ８半導体では、ソース・ドレインＶＣＡＧを
１９いたゲートグヤンネル長２μクル以下のＮＭＯＦ１
ｇ半導体装置は量産ちれているものの、ソース・ドレイ
ンに”Ｂ　’に用い７（ｐｏｈ）ランジスタとソース争
ドレインに”Ｐ　ｋ用い［Ｎａｈ　トランジスタとを備
えた０ＭＯ８型半導体装置においては、ソース・ドレイ
ン拡散深さく以下Ｘｊ　とＩピす）の浅い制御が内部な
た。ｂ、バンチスルーによるゲートチャンネル長限界が
６μｍ程度であった。しかるにＣＭＯ８半導体装斬は］
（’ｋＡ　ＯＳ半導体装置に比べ、小型化の点で劣ると
いう欠点があった。In the conventional 0MO8 semiconductor, the source/drain VCAG was 19, but the gate channel length was less than 2 μk.
Although mass production of g semiconductor devices has declined, in the case of 0MO8 type semiconductor devices equipped with "B" transistors for the source and drain and "Pk" transistors for the source and drain, The shallow control of the drain diffusion depth (below Xj and I) is internal. b. The gate channel length limit due to bunch through was approximately 6 μm. However, CMO8 semiconductor equipment is]
(Compared to 'kA OS semiconductor devices, it had the disadvantage of being inferior in terms of miniaturization.

本発明は、かかる従来技術の欠点をなくする１ζめＫ、
ｘｊの浅い制御を可能にし、ソース争ドレインＶＣ”Ｂ
を用い＊Ｐｃｈ）ランジスタとソース・ドレインに３１
ｐｌ用い１こＮａｈ）ランジスタと’（ｒｌｉｌえ７（
０）ｔ＋　０８型半導体装置において、ゲートチャンネ
ル長が２ｔｒｍ以下の０Ｍ０ＥＩ型半導体装置を提供す
る。The present invention eliminates the drawbacks of the prior art,
Enables shallow control of xj, source conflict drain VC”B
*Pch) 31 for transistor and source/drain
pl use 1 ko Nah) transistor and'(rliile 7(
0) In the t+08 type semiconductor device, an 0M0EI type semiconductor device having a gate channel length of 2 trm or less is provided.

以下、実施例谷・用いて詳細に説明する。Hereinafter, a detailed explanation will be given using an example.

第１図は、従来及び本発明の多結晶ンリコンゲ−トＯＭ
　ＯＳ半導体装置の製作工程であり、ｐａｈソース魯ド
レイン形成１１Ｂイオン注入とＮｏｈソース・ドレイン
形成：ｌｉｐミルイオン後のアニールは従来工程でばＮ
２熱拡散アニール（ｎ）で行ない、一方、本発明の実施
例によれば、表面層を数秒間のランプ加熱（＋）により
了ニールする。FIG. 1 shows conventional and inventive polycrystalline recombination gate OMs.
This is the manufacturing process of an OS semiconductor device, and the annealing after the lip mill ionization is the conventional process of N ion implantation and Noh source/drain formation.
2 thermal diffusion annealing (n), while according to an embodiment of the invention the surface layer is annealed by lamp heating (+) for a few seconds.

第２図は、多結晶シリコンゲート１−′ｃｈトランジス
タの断面図であり、ソース・ドレインの拡散深さをｘｊ
（Ｂ）で示す。ソース・ドレインリボロンＢで形成さｊ
ｌている。FIG. 2 is a cross-sectional view of a polycrystalline silicon gate 1-'ch transistor, with the source/drain diffusion depth xj
Indicated by (B). Source/drain formed from Riboron B
I'm there.

３ｔ６図は、多結晶シリコンゲート１ｎｃｈ）ランジス
タの断面図であり、ソース−ドレインの拡散深さをｘｊ
（Ｐ）で示す。ソース・ドレインはリンＰで形成されて
いる。Figure 3t6 is a cross-sectional view of a polycrystalline silicon gate (1 nch) transistor, with the source-drain diffusion depth xj
Indicated by (P). The source and drain are made of phosphorus.

不発明のトランジスタの断■溝造は、ｘｊ（Ｂ）とｘｚ
　（Ｐ）がともに各々従来のトランジスタのｘｊ（Ｂ）
　　とｘｊ（ｐ）　より０．５７１　ｒｎ程就浅く、従
ってＰｃｈＩＮ？ｌｂ共にゲート長が１μｍ８度短；ｏ
１りなり、２／ｉｒｎ弱のゲート長を持つＣ１・ＡＯ８
半導体装齢左回能となる。Uninvented transistor disconnect ■ Mizozo is xj (B) and xz
(P) are both xj (B) of each conventional transistor
and xj(p) is about 0.571 rn, so PchIN? Both lb and gate length are 1 μm 8 degrees shorter; o
C1/AO8 with a gate length of 1 or less than 2/irn
Semiconductor age becomes left gynecological.

第４図〜第９図は、表面ヒーター塩ｉＪｊ　１３　Ｕ　
０℃でランプ加熱アニールを数秒間合な゛った時のソー
ト抵抗及びＸｊを示し、Ｎ２熱拡散アニールを行なった
時のソート抵抗及びＸｊ　と比較している。Figures 4 to 9 show surface heater salt iJj 13 U
The sort resistance and Xj when lamp heat annealing was performed for several seconds at 0° C. are shown, and compared with the sort resistance and Xj when N2 thermal diffusion annealing was performed.

第４図は、ボｏ　ｙ　４　Ｘ　１０１５ｃｍ−２＃　４
０　ＫｅＶ”ｉ注入した時の７−ト抵抗とランプ加熱時
間との相関である。７は、１０００℃２０分のＮ２熱拡
散アニールを行なった時の７−ト抵抗で、約２７Ω／口
である。ラング加熱全６秒行なえば、熱アニールと同程
度になる。Figure 4 shows the size of the bow 4 x 1015cm-2#4
This is the correlation between the 7-t resistance and the lamp heating time when 0 KeV"i is implanted. 7 is the 7-t resistance when N2 thermal diffusion annealing is performed at 1000℃ for 20 minutes, and it is approximately 27 Ω/mouth. Yes, if Lang heating is performed for a total of 6 seconds, it will be about the same as thermal annealing.

第５図は、す７４Ｘ１０”ｔｍ−２＊４０ＫｅＶ　ｆ注
入した時のソート抵抗とランプ加熱時間との相関である
。８は１０００℃２０分のＮ２熱拡散アニールケ行なっ
た時の／−ト抵抗で、約２２　Ｌｉ／口である。ランプ
加熱を６秒行なえば、熱了ニールと同程度になる。Figure 5 shows the correlation between sort resistance and lamp heating time when 74 x 10" tm-2*40 KeV f was implanted. 8 is the /-t resistance when N2 thermal diffusion annealing was performed at 1000°C for 20 minutes. , about 22 Li/mouth.If lamp heating is performed for 6 seconds, it will be about the same level as heating after heating.

第６図は、７ｆ：　ｏ　７４　×１０１５釧−”　＊　
４０　Ｋ　ｅ　Ｖ　ｆｆｉ注入した時のｘｊ（Ｂ）とラ
ンプ加熱時間との相関である。９は１０００℃２０分の
Ｎ２熱拡散アニールを行なった時のｘｊ（Ｂ）で、約１
μｍである。Figure 6 shows 7f: o 74 x 1015 sen -” *
This is a correlation between xj (B) and lamp heating time when 40 K e V ffi is injected. 9 is xj (B) when performing N2 thermal diffusion annealing at 1000°C for 20 minutes, which is approximately 1
It is μm.

第７図は、リン４　Ｘ　１０１５ａｎ−２＊　４０　Ｋ
ｅＶ　’ｆ注入した時のＸｊ（Ｐ）とランプ加熱時間と
の相関である。１０（ｄ１０００℃２ｏ分のＮ２熱拡散
アニール會行なった時のスｊ（Ｐ）で、約１μπＬであ
る。Figure 7 shows phosphorus 4 x 1015 an-2* 40 K
This is the correlation between Xj(P) and lamp heating time when eV'f is injected. 10 (d) when N2 thermal diffusion annealing is performed at 1000° C. for 20 minutes, the value of Sj(P) is approximately 1 μπL.

第８図は、ホｏ　７４　Ｘ　１０”ｃｍ−”　ノ時のｘ
ｊ（Ｂ）と打ち込みエネルギーとの相関であり、ランプ
加熱によればＸ、１（Ｂ）ユ０．４１ｔ　ｇｎ　　を提
供できる。Figure 8 shows x at 74 x 10"cm-"
It is a correlation between j(B) and implantation energy, and lamp heating can provide X,1(B) u0.41tgn.

第９図は、リン４　Ｘ　１０”ｃｒｎ−２の時のｘｊ（
ｐ）と打ち込みエネルギーとの相関であり、ランプ加熱
によりばｘｊ（Ｐ）：；０．４μｍ　を提供できる。Figure 9 shows xj(
It is a correlation between p) and implantation energy, and lamp heating can provide xj(P):;0.4 μm.

第８図・第９図は、ランプ加熱６秒でアニールを行なっ
た。In FIGS. 8 and 9, annealing was performed with lamp heating for 6 seconds.

以上から、ランプ加熱アニールを用いることによりＮ２
拡散アニールより活性化が大きく、シがもｐｏｈと１Ｊ
ａｈのどちらのトランジスタの拡散深さもｘ３＝０．４
μｍに制御可能になり、ｐａｈ　ｍ　１Ｊｃｈとも［２
μｍ以下のゲート長を持つ０ＭＯ８型半導体装置が提供
できる。From the above, by using lamp heating annealing, N2
Activation is larger than diffusion annealing, and Shigamo poh and 1J
The diffusion depth of both transistors of ah is x3=0.4
μm controllable, pah m 1Jch [2
It is possible to provide an 0MO8 type semiconductor device having a gate length of less than μm.

【図面の簡単な説明】[Brief explanation of the drawing]

８ｇ１図・・・従来及び本発明による０ＭＯ８半導体装
置の製造工程 第２１図・・・多結晶シリコンゲートＰｏｈ）ランジス
タの断面構造図。 　５− 第６図・・・多結晶ンリコンゲー）ＩＪｃｈ）ランジス
タの断面構造図。 第４図〜第９図・・・ランプ加熱アニール’ｘ　行ｙつ
１６時のソート抵抗及びＸｊの実験測定値。 １・・・多結晶シリコン ２・・・ｐｏｈソース拳ドレインボロン拡散層６・・・
素子分離領域　　　４・・・ｎ　Ｗｅｌｌ領域６・・・
Ｎｃｈソース・ドレインリン拡散層領域７・・・Ｎ２熱
拡散アニール１０ＵＯ℃２０分を行なった時のソート抵
抗 ８・・・Ｎ２熱拡散アニール１０００℃２０分を行なっ
た時のソート抵抗 ９・・・Ｎ２熱拡散アニールＩＵＯＩＪｔ？、２０分を
行なった時のｘｊ（Ｂ） １０・・・Ｎ２熱拡散アニール１０００１：２０分を行
なった時のｘｊ（Ｐ）。 以上 出願人　株式会社　趣訪精工舎 代理人　弁理士　最上　　務 　６− 第８図 ｊ丁シυ−リＥｎ弓と　（ヒフ２ 第９図Fig. 8g1... Manufacturing process of OMO8 semiconductor device according to conventional and present invention Fig. 21... Cross-sectional structural diagram of polycrystalline silicon gate Poh) transistor. 5- Fig. 6... Cross-sectional structural diagram of a polycrystalline transistor (IJch) transistor. Figures 4 to 9... Experimental measurement values of sort resistance and Xj when lamp heating annealing 'x rows y 16 times. 1... Polycrystalline silicon 2... POH source drain boron diffusion layer 6...
Element isolation region 4...n Well region 6...
Nch source/drain phosphorus diffusion layer region 7...Sort resistance when N2 thermal diffusion annealing is performed at 10UO°C for 20 minutes 8...Sort resistance when N2 thermal diffusion annealing is performed at 1000°C for 20 minutes 9... N2 thermal diffusion annealing IUOIJt? , xj (B) when performed for 20 minutes 10... N2 thermal diffusion annealing 10001: xj (P) when performed for 20 minutes. Applicant Shuwa Seikosha Co., Ltd. Agent Patent Attorney Tsutomu Mogami 6- Figure 8

Claims (1)

【特許請求の範囲】 集積回路をＭ成する絶縁ゲート型電界効果トランジスタ
素子において、 ソース争ドレインがボロンで形成された、ゲート長２μ
ｍ以下のＰチャンネルトランジスタと、ソース・ドＩ／
インがリンで形Ｈ，された、ゲート長２ノロｎ以下のＮ
チャンネルトランジスタと牙、備えてなることを特徴と
するＯ　Ｍ　ＯＳ型半導体装置。[Claims] In an insulated gate field effect transistor element constituting an integrated circuit, the source and drain are made of boron, and the gate length is 2μ.
m or less P-channel transistor and source-do I/
In is shaped like H with phosphorus, and N has a gate length of 2 noron or less.
An OMOS type semiconductor device comprising a channel transistor and a fan.
JP56194974A 1981-12-03 1981-12-03 Cmos semiconductor device Granted JPS5896763A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56194974A JPS5896763A (en) 1981-12-03 1981-12-03 Cmos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56194974A JPS5896763A (en) 1981-12-03 1981-12-03 Cmos semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP1033138A Division JPH02353A (en) 1989-02-13 1989-02-13 Cmos type semiconductor device

Publications (2)

Publication Number Publication Date
JPS5896763A true JPS5896763A (en) 1983-06-08
JPH0221148B2 JPH0221148B2 (en) 1990-05-11

Family

ID=16333434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56194974A Granted JPS5896763A (en) 1981-12-03 1981-12-03 Cmos semiconductor device

Country Status (1)

Country Link
JP (1) JPS5896763A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601862A (en) * 1983-06-20 1985-01-08 Seiko Epson Corp Manufacture of semiconductor device
JPS6077419A (en) * 1983-10-04 1985-05-02 Seiko Epson Corp Manufacture of semiconductor device
JPH0629316A (en) * 1993-01-18 1994-02-04 Seiko Epson Corp Manufacture of semiconductor device
US6218270B1 (en) 1998-03-04 2001-04-17 Nec Corporation Method of manufacturing semiconductor device having shallow junction
JP2002332073A (en) * 2001-05-08 2002-11-22 Rootarii Kk Fine punch sheet

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
APPL PHYS LETT INCOHERENT-LIGHT-FLASH ANNEALING OF PHOSPHORUS-IMPLANTED SILICON=1980 *
JAPANESE JOURNAL OF APPLIED PHYSICS RADIATION ANNEALING OF BORON-IMPLANTED SILICON WITH A HALOGEN LAMP=1980 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601862A (en) * 1983-06-20 1985-01-08 Seiko Epson Corp Manufacture of semiconductor device
JPH0526343B2 (en) * 1983-06-20 1993-04-15 Seiko Epson Corp
JPS6077419A (en) * 1983-10-04 1985-05-02 Seiko Epson Corp Manufacture of semiconductor device
JPH0629316A (en) * 1993-01-18 1994-02-04 Seiko Epson Corp Manufacture of semiconductor device
US6218270B1 (en) 1998-03-04 2001-04-17 Nec Corporation Method of manufacturing semiconductor device having shallow junction
JP2002332073A (en) * 2001-05-08 2002-11-22 Rootarii Kk Fine punch sheet

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Publication number Publication date
JPH0221148B2 (en) 1990-05-11

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