JPH0526343B2 - - Google Patents
Info
- Publication number
- JPH0526343B2 JPH0526343B2 JP58110519A JP11051983A JPH0526343B2 JP H0526343 B2 JPH0526343 B2 JP H0526343B2 JP 58110519 A JP58110519 A JP 58110519A JP 11051983 A JP11051983 A JP 11051983A JP H0526343 B2 JPH0526343 B2 JP H0526343B2
- Authority
- JP
- Japan
- Prior art keywords
- fet
- mos
- ion
- type
- ions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010438 heat treatment Methods 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 230000000295 complement effect Effects 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 6
- -1 31P ions Chemical class 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 238000009792 diffusion process Methods 0.000 description 11
- 239000013078 crystal Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 230000007774 longterm Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000005596 ionic collisions Effects 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
- Y02T10/00—Road transport of goods or passengers
- Y02T10/10—Internal combustion engine [ICE] based vehicles
- Y02T10/12—Improving ICE efficiencies
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
本発明は、MOS型FETの製造方法に関する。
特に、相補型MOS・FETからなる高集積度LSI
に関するものであり、ソース及びドレイン領域と
なる不純物拡散層を低温短時間アニールにより素
子の高密度化に対応でき、更に結晶欠陥によるリ
ーク電流の少ない半導体装置を提供することを目
的とする。
従来、シリコン・ゲート相補型MOS・FETか
らなるLSI製造において、P型MOS・FETのソ
ース・ドレイン領域には、高濃度(1.0×1015cm-2
以上)11Bイオンが注入され、n型MOS・FETの
ソース・ドレイン領域には高濃度(1.0×1015cm-2
以上)75Asイオンが注入され、該イオン注入層は
高温長時間(例えば100℃30分)熱処理アニール
される。しかしながら、11B及び75Asは、高温長
時間アニールで100%活性化するものの、11B注入
拡散層は、横及び深さ方向に拡がり接合深さは
0.5μm以上の大きさになりソース・ドレインのパ
ンチスルーを引きおこし、P型MOS・FETの微
細化を防げた。又、75Asイオン注入層は、注入イ
オンの質量がシリコン基板のSiに比べて大きく、
注入時にイオン衝突による結晶欠陥を引きおこ
し、n型接合におけるリーク電流が大きく、欠陥
を回復しリーク電流を減らすためには、どうして
も高温アニールが必要である。従つて、従来の相
補型MOS・FET製造方法で、微細化が不可能で
しかも欠陥によるリーク電流の少ないLSIの製造
ができない。
本発明は、かかる従来の欠点を取り除き、欠陥
によるリーク電流が少なくかつ微細化が可能な相
補型MOS・FETの製造方法を与えることを目的
とする。
上記目的を達成するため、本発明では、P型
MOS・FETのソース・ドレイン領域には、BF2
イオンを1×1015cm-2以上注入し、n型MOS・
FETのソース・ドレイン領域には31Pイオンを1
×1015cm-2以上注入し、イオン注入層のアニール
を900℃以下の低温で、1分以内の短時間熱処理
によつて行なうことを特長としている。
以下、実施例を用いて詳細に説明する。表2
は、従来の相補型MOS・FET製造のフロー・チ
ヤートである。ウエル・フイールド膜・ゲート
膜、及びPolysiゲート電極形成後、P型MOS・
FETのソース・ドレイン領域に11Bイオンを注入
し、N型MOS・FETのソース・ドレインに75As
イオンを注入後、拡散炉を用いた高温長時間熱処
理を行ないイオン注入層の結晶回復及び活性化を
行なつていた。従来の製造方法では第1図に示す
ごとく11Bイオンの活性化のためには900℃以上
の高温熱処理が必要であり、また75Asの質量数
が大きいためシリコン基板表面のダメージが大き
く、ダメージによる拡散接合のリーク電流低減の
ため高温長時間の熱処理アニールを必要とした。
しかるに従来の高温長時間熱処理(例えば1000℃
30分)では、ボロンの拡散長が大きくなり、拡散
接合深さ及び横拡がりが大きくなり、ソース・ド
レイン間のパンチスルーのためP型MOS・FET
の縮小化に制限を与えている。
表1は、本発明による相補型MOS・FET製造
のフロー・チヤートである。ウエル・フイールド
膜・ゲート膜、及びPolySiゲート電極形成後、
P型MOS・FETのソース・ドレイン領域にBF2
イオンを1×1015cm-2以上注入し、N型MOS・
FETのソース・ドレイン領域に31Pイオンを1×
1015注入後、ハロゲン・ランプ、グラフアイト・
ヒーターなどにより低温短時間熱処理を行ないイ
オン注入層の結晶回復及び活性化を行なう。本発
明において、BF2を1×1015cm-2以上注入するの
は、注入層がアモルフアス化するために必要だか
らである。また31Pを1×1015cm-2以上注入する
ことも同じ理由による。BF2または31Pによりア
モルフアス化されたイオン注入層の結晶回復は
700℃以上の熱処理で可能であり、第1図に示す
ようにBF2または31Pイオンの活性化は800℃以上
の熱処理で100%活性化する。第1図におけるア
ニール温度とシート抵抗の相関は、イオン注入量
が1.0×1015cm-2アニール時間が10秒の場合であ
る。従つて、BF2または31Pイオン注入によりア
モルフアス化されたイオン注入層は、900℃以下
の低温かつ1分以内の短時間熱処理でアニール可
能である。900℃以下の温度で1分以内で熱処理
はボロンの拡散再分布はない。しかも、n型、P
型のイオンは質量数がSiと大きくちがわないた
め、低温短時間熱処理により拡散接合のリーク電
流は小さい。従つて、本願発明によれば、イオン
半径の小さいボロンの替わりに二弗化ボロンをイ
オン注入することにより、イオン注入層のシリコ
ン結晶構造が乱され、すなわちアモルフアス化さ
れることにより低温で短時間のアニールが可能と
なり、拡散層の拡散再分布を抑制できるのでP型
MOS・FETの縮小が可能になるという効果を有
する。更にBF2およびPの質量数と基板材料のSi
の質量数とあまり差が無いので、イオン注入時の
イオンの衝突による結晶欠陥が少なくなるので
900℃以下の低温で短時間、例えば1分以下のア
ニールにおいても拡散接合のリーク電流を低く抑
えることができ、信頼性の高い半導体装置を提供
することが出来るという効果がある。
The present invention relates to a method for manufacturing a MOS FET.
In particular, highly integrated LSIs consisting of complementary MOS/FETs
It is an object of the present invention to provide a semiconductor device which can cope with higher density of elements by annealing impurity diffusion layers which become source and drain regions at a low temperature for a short time, and further has less leakage current due to crystal defects. Conventionally, in the manufacture of LSIs consisting of silicon gate complementary MOS/FETs, the source/drain regions of P-type MOS/FETs are coated with a high concentration (1.0×10 15 cm -2
11 B ions are implanted into the source and drain regions of n-type MOS/FETs at a high concentration (1.0×10 15 cm -2
75 As ions are implanted, and the ion-implanted layer is annealed at high temperature for a long time (for example, 100° C. for 30 minutes). However, although 11B and 75As are 100% activated by high-temperature and long-term annealing, the 11B implanted and diffused layer spreads laterally and in the depth direction, and the junction depth decreases.
It became larger than 0.5 μm, causing source/drain punch-through and preventing miniaturization of P-type MOS/FET. In addition, in the 75 As ion-implanted layer, the mass of implanted ions is larger than that of Si in the silicon substrate.
Crystal defects are caused by ion collision during implantation, resulting in a large leakage current at the n-type junction, and high-temperature annealing is absolutely necessary to recover the defects and reduce the leakage current. Therefore, conventional complementary MOS/FET manufacturing methods cannot be used to manufacture LSIs that cannot be miniaturized and have less leakage current due to defects. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a complementary MOS/FET which eliminates such conventional drawbacks, causes less leakage current due to defects, and allows miniaturization. In order to achieve the above object, the present invention provides P-type
BF 2 is used in the source and drain regions of MOS/FET.
By implanting ions of 1×10 15 cm -2 or more, n-type MOS・
31P ions are added to the source and drain regions of the FET.
The ion-implanted layer is implanted at a rate of ×10 15 cm -2 or more, and the ion-implanted layer is annealed at a low temperature of 900°C or less by a short heat treatment lasting less than 1 minute. Hereinafter, it will be explained in detail using examples. Table 2
is a flow chart of conventional complementary MOS/FET manufacturing. After forming the well field film, gate film, and Polysi gate electrode, P-type MOS
11 B ions are implanted into the source/drain region of the FET, and 75 As is implanted into the source/drain of the N-type MOS/FET.
After ion implantation, high temperature and long-term heat treatment using a diffusion furnace was performed to recover and activate the crystals of the ion implanted layer. In the conventional manufacturing method, as shown in Figure 1, high-temperature heat treatment of 900℃ or higher is required to activate 11 B ions, and the large mass number of 75 As causes significant damage to the silicon substrate surface. In order to reduce leakage current in diffusion bonding, high-temperature and long-term heat treatment annealing was required.
However, conventional high-temperature, long-term heat treatment (e.g. 1000℃)
30 minutes), the boron diffusion length increases, the diffusion junction depth and lateral spread increase, and the punch-through between the source and drain increases the P-type MOS/FET.
This limits the downsizing of the . Table 1 is a flow chart of complementary MOS/FET manufacturing according to the present invention. After forming the well field film, gate film, and PolySi gate electrode,
BF 2 in the source and drain regions of P-type MOS/FET
By implanting ions of 1×10 15 cm -2 or more, N-type MOS
1x 31P ions in the source/drain region of the FET
10 15 After injection, halogen lamp, graphite
A low-temperature, short-time heat treatment is performed using a heater or the like to recover and activate the crystals of the ion-implanted layer. In the present invention, the reason why BF 2 is implanted at 1×10 15 cm −2 or more is necessary to make the implanted layer amorphous. The same reason also applies to injecting 1×10 15 cm -2 or more of 31 P. Crystal recovery of the ion-implanted layer amorphized by BF 2 or 31 P is
This is possible with heat treatment at 700°C or higher, and as shown in Figure 1, BF 2 or 31 P ions can be activated 100% by heat treatment at 800°C or higher. The correlation between annealing temperature and sheet resistance in FIG. 1 is when the ion implantation amount is 1.0×10 15 cm −2 and the annealing time is 10 seconds. Therefore, the ion-implanted layer made amorphous by BF 2 or 31 P ion implantation can be annealed by heat treatment at a low temperature of 900° C. or lower and for a short time of less than 1 minute. Heat treatment at a temperature below 900°C within 1 minute does not cause boron diffusion redistribution. Moreover, n-type, P
Since the mass number of type ions is not significantly different from that of Si, leakage current in diffusion bonding is small due to low-temperature, short-time heat treatment. Therefore, according to the present invention, by ion-implanting boron difluoride instead of boron, which has a small ionic radius, the silicon crystal structure of the ion-implanted layer is disturbed, that is, the silicon crystal structure is made amorphous, so that the silicon crystal structure can be ion-implanted at low temperatures for a short period of time. P-type annealing is possible, and diffusion redistribution of the diffusion layer can be suppressed.
This has the effect of making it possible to downsize the MOS/FET. Furthermore, the mass number of BF 2 and P and the substrate material Si
Since there is not much difference between the mass number of
Even when annealing is performed at a low temperature of 900° C. or less for a short time, for example, one minute or less, the leakage current of the diffusion bond can be suppressed to a low level, and a highly reliable semiconductor device can be provided.
【表】
製造のフロー・チヤート
[Table] Manufacturing flow chart
【表】【table】
【表】
フロー・チヤート
[Table] Flow chart
第1図……ハロゲン・ランプ短時間アニールに
よる拡散層のシート抵抗とアニール温度の相関を
示す図。
FIG. 1: A diagram showing the correlation between the sheet resistance of the diffusion layer and the annealing temperature obtained by short-time annealing using a halogen lamp.
Claims (1)
造方法において、前記相補型MOS・FETの構成
要素であるP型MOS・FET形成領域の一部に
BF2イオンを1×1015cm-2以上注入して前記P型
MOS・FETのソース領域及びドレイン領域とな
るBF2イオン注入層を形成する工程、前記相補型
MOS・FETの構成要素であるN型MOS・FET
形成領域の一部に31Pイオンを1×1015cm-2以上
注入して前記N型MOS・FETのソース領域及び
ドレイン領域となるPイオン注入層を形成する工
程、前記BF2イオン注入層及び前記Pイオン注入
層を900℃以下の温度で短時間の熱処理アニール
をおこなう工程を有することを特徴とする半導体
装置の製造方法。1. In a method for manufacturing a semiconductor device having a complementary MOS/FET, a part of the P-type MOS/FET formation region which is a component of the complementary MOS/FET is
By implanting BF 2 ions of 1×10 15 cm -2 or more, the P-type
The step of forming a BF 2 ion implantation layer that will become the source region and drain region of the MOS/FET, the complementary type
N-type MOS/FET, a component of MOS/FET
a step of implanting 31P ions of 1×10 15 cm -2 or more into a part of the formation region to form a P ion implantation layer that will become the source region and drain region of the N-type MOS/FET, the BF 2 ion implantation layer; and a step of subjecting the P ion-implanted layer to short-time heat treatment annealing at a temperature of 900° C. or lower.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58110519A JPS601862A (en) | 1983-06-20 | 1983-06-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58110519A JPS601862A (en) | 1983-06-20 | 1983-06-20 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS601862A JPS601862A (en) | 1985-01-08 |
JPH0526343B2 true JPH0526343B2 (en) | 1993-04-15 |
Family
ID=14537848
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58110519A Granted JPS601862A (en) | 1983-06-20 | 1983-06-20 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS601862A (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0831603B2 (en) * | 1986-07-07 | 1996-03-27 | セイコー電子工業株式会社 | Manufacturing method of PMIS transistor |
JPH0661738U (en) * | 1993-02-03 | 1994-08-30 | 八千矛化学株式会社 | Tube body container mouth |
US6342275B1 (en) | 1993-12-24 | 2002-01-29 | Seiko Epson Corporation | Method and apparatus for atmospheric pressure plasma surface treatment, method of manufacturing semiconductor device, and method of manufacturing ink jet printing head |
JPH08250488A (en) * | 1995-01-13 | 1996-09-27 | Seiko Epson Corp | Device and method for plasma treatment |
JP3959745B2 (en) * | 1995-04-07 | 2007-08-15 | セイコーエプソン株式会社 | Surface treatment equipment |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5896763A (en) * | 1981-12-03 | 1983-06-08 | Seiko Epson Corp | Cmos semiconductor device |
-
1983
- 1983-06-20 JP JP58110519A patent/JPS601862A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5896763A (en) * | 1981-12-03 | 1983-06-08 | Seiko Epson Corp | Cmos semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS601862A (en) | 1985-01-08 |
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