JPS5893255A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an electrode wiring layer having a flat surface by covering a semiconductor substrate with an insulating film, opening a hole, forming a conductor film made of Si, high melting point metal on the overall surface including the hole, etching the allowing the conductor film to remain only on the opened side wall, and burying a metal film thereat. CONSTITUTION:An SiO2 film 2 is covered on an Si substrate 1, a photoresist film 3 of the prescribed pattern is covered on the film 2, and with the film 3 as a mask it is etched with fluoric acid series aqueous solution or CF4-H2 series gas, thereby opening holes at the film 2. Then the film 3 is removed, a polycrystalline Si film 4 is accumulated on the overall surface, the film 4 is allowed to remain by reactive ion etching with BBr3-Cl2 gas only on the side surfaces of the holes of the film 2, and the other portion is removed. Thereafter, the interior of the holes of the film 2 in which the film 4 adhered only to the side surfaces of the holes is buried by a pressure reduction method with W metal film 5 and is used as the electrode wiring layer. Subsequently, the Al-Si wiring film 6 which is contacted with the film 5 is covered, a window is opened corresponding to the part of the film 5, and an oxidized film 7 is covered over the entire surface including the window.

Description

【発明の詳細な説明】 （１）発明の属する技術分野 本発明は半導体装置の製造方法に係り，特に電極配線の
形成方法を改良した半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a method for forming electrode wiring is improved.

（２）従来技術とその問題点 従来より半導体素子の電極及び配線材料として多結晶シ
リコン（Ｐｏｌｙ−Ｓｉ）及びアルミニウム（Ａ−ｌ）
が用いられてきた。特に配線材料としてはＡｌが広く用
いられて来ているが、近年半導体集積回路の素子の微細
化と高集積化及び回路の高速変化に供なり、新しい配線
材料が望まれている。この要望に対ｌ〜で現在注目され
ている材料が、高融点金属及びその硅化物である。高融
点金属はＭに比べ、比抵抗値はわずかに高いものの，　
Ｐｏｌｙ−Ｓｉに比べて十分に低く、しかも高温処理が
可能という利点があり、ＭＯＳ型デバイスの自己整合法
への適用多層配線構造にも利用できる。更に高融点金属
を硅素との化合物にすることに・よって、゛耐酸性化す
ることができる。すでに高融点金属硅化物は。(2) Prior art and its problems Polycrystalline silicon (Poly-Si) and aluminum (A-1) have traditionally been used as electrode and wiring materials for semiconductor devices.
has been used. In particular, Al has been widely used as a wiring material, but in recent years, new wiring materials are desired as semiconductor integrated circuit elements become smaller and more highly integrated, and circuits change rapidly. Materials that are currently attracting attention in response to this demand are high-melting point metals and their silicides. Although high melting point metal has a slightly higher specific resistance value than M,
It has the advantage that it is sufficiently lower than Poly-Si and can be processed at high temperatures, and can also be used for multilayer wiring structures applied to self-alignment methods of MOS type devices. Furthermore, by forming a compound with a high melting point metal and silicon, acid resistance can be achieved. There are already high melting point metal silicides.

Ｐｏｌｙ−Ｓｔにとって代わり、実用化されてぃるりと
ころで、これらの高融点金属やその硅化物の形成方法に
は、主に蒸着法が採用されているが、最近ＣＶＤ法によ
る高融薇金属膜の選択的形成方法が開発されている。こ
の方法によると、第１図に示すように、シリコン（Ｓｉ
）ｌが露出１−ている面のみｅＣ高融点金属膜が形成さ
れる。この技術により、マスク合わせなＩ−に高融点金
属配線層を形成することが出来るとともに、この配線層
を埋め込むこともでき、半導体装１ｄの高集積化で重要
な平坦化に大きな役割を果すことができる。現在この技
術は主にコンタクトホールの段差を小さくする埋め込み
として使われ、成極配線の段切れを防止している。It has been put into practical use as a replacement for Poly-St. However, the vapor deposition method is mainly used to form these high melting point metals and their silicides, but recently the CVD method has been used to selectively form high melting point metal films. Formation methods have been developed. According to this method, as shown in FIG.
) The eC high melting point metal film is formed only on the exposed surface. With this technology, it is possible to form a high melting point metal wiring layer on I- without matching the mask, and it is also possible to embed this wiring layer, which plays a major role in planarization, which is important for the high integration of semiconductor devices 1d. I can do it. Currently, this technology is mainly used as a filler to reduce the level difference in contact holes, and to prevent breakage in the polarization wiring.

このように高融点金属膜をＣＶｌ）法により形成する技
術は、上述のような特徴を持ち、有望視されているが、
まだ幾つかの問題点を残している。The technology of forming a high-melting point metal film using the CVl method has the above-mentioned characteristics and is considered promising.
There are still some problems left.

１つＵｍ１図（Ａ）の部分の形状である。図のように、
高融薇金属膜５は絶縁膜２の間を埋め込むことが出来ず
、悪いことには（〜の油分のように、するどい大きな溝
を作ってしまい、次に形成される電極配線層の段切れを
引き起こす。One Um1 is the shape of the part shown in Figure (A). As shown,
The high-melting metal film 5 cannot fill in the space between the insulating films 2, and worse, it creates large grooves (like the oil in ~), causing breaks in the electrode wiring layer to be formed next. .

また、高融点金属膜５の厚さは、２０００Ａ程度しか成
長せず、今後半導体装置の高集積化に伴なうコンタクト
ホールの深さを埋め込み、電極配線層を平坦化するには
、まだ改良が必曹である。In addition, the thickness of the high melting point metal film 5 has only grown to about 2000 Å, and it still needs to be improved in order to fill the depth of contact holes and flatten the electrode wiring layer as semiconductor devices become more highly integrated in the future. is essential.

（３）発明の目的 本発明はこのように現在ＣＶ　Ｉ）法による高融点金属
膜の形成方法が抱えている諸問題を解決するためになさ
れたもので、これによって例えばコンタクトホールＶ（
形成する高融点金属膜の形状を滑らかにし、更に膜を厚
くすることが出来、埋め込み平坦化を実現し、電極配線
層の段切れを防止し配線層の信頼性を高めるとともに、
高集積化に伴なう微細化をも可能にするものである。(3) Purpose of the Invention The present invention has been made in order to solve the various problems currently encountered in the current method of forming a high melting point metal film by the CV I) method.
The shape of the high melting point metal film to be formed can be made smoother, the film can be made thicker, it can be buried flat, it can prevent breakage in the electrode wiring layer, and it can increase the reliability of the wiring layer.
This also enables miniaturization that accompanies higher integration.

（４）発明の概要 即ち、本発明ｖ′１ＣｖＤ法で形成される膜の被覆特性
と、反応性イオンエツチング（ＲＩＥ）の異方性を利用
して改善１−だものである。(4) Summary of the invention: This invention is an improvement 1- by utilizing the coating properties of the film formed by the CvD method and the anisotropy of reactive ion etching (RIE).

ＩＩ、。II.

ＣＶＤ法で形成される時は、下地のどの面に対しても同
じ厚さで堆積す６という性質があシ、また反応性イオン
エツチングは異方的にエツチング行なうものである。When it is formed by CVD, it has the property that it is deposited to the same thickness on any surface of the underlying layer, and reactive ion etching is anisotropic etching.

これらから例えば第２図（ａ）のようにシリコン基板ｌ
Ｉ上に二酸化硅素膜２を形成加工した後、、　ＣＶＤ法
によって多結晶シリコン膜（Ｐｏ１ｙ−８ｉ）　４を堆
積すると、表面（図では上方）から見た場合、二酸化硅
素膜２の側面（Ｂ）は、Ｐｏ１ｙ−８ｉ膜４が平面部（
Ｃ）の２倍の厚さに堆積していることが判る。この状態
で反応性イオンエツチングを行なうと異方性エツチング
によって二１俊化硅累膜２の側面にＰｏ１ｙ−８ｉ膜４
が第２図（ｈ）のように残り、しかもこの形状は非常に
なだらかである。この後、ＣＶＤ法により高融点金属を
形成すると、高融薇金属膜の成長が第２図（Ｃ）に示す
ように、三方向から同時に始干るため、膜の成長が速く
膜厚を厚くすることができるとともに膜厚の均一性もよ
い膜が得られるっ（５）発明の実施例 以下に本発明の実施例について述べる。From these, for example, as shown in FIG. 2(a), a silicon substrate l
After forming and processing the silicon dioxide film 2 on the silicon dioxide film 2, a polycrystalline silicon film (Poly-8i) 4 is deposited by the CVD method, and when viewed from the surface (from above in the figure), the side surface (B ), the Po1y-8i film 4 has a flat surface (
It can be seen that the thickness is twice that of C). When reactive ion etching is performed in this state, the Po1y-8i film 4 is formed on the side surface of the 21 atomized silicon layer 2 by anisotropic etching.
remains as shown in FIG. 2(h), and this shape is very gentle. After this, when a high melting point metal is formed by the CVD method, the growth of the high melting metal film starts from three directions simultaneously as shown in Figure 2 (C), so the film grows quickly and the film thickness can be increased. (5) Examples of the Invention Examples of the present invention will be described below.

第３図（ａ）に示すようにシリコン基板１に例えば厚さ
〜１μｍの二酸化硅素膜２を形成し、その上に写真蝕刻
法によりフォトレジスト膜３のパターン形成し、これを
マスクにし弗酸系水溶液或いはＣＦ　４−Ｈ２系ガスで
エツチングを行ない、絶縁層を形成する。フォトレジス
ト膜３を除去した後、第３図（ｂ）に示すように例えば
厚さ０．５　μｍ　（７）　ＰＯ１ｙ−８ｉ膜４を形成
し、ＢＢｒ３−Ｃ１２ガスを用い反応性イオンエツチン
グを行なう。すると、第３図（Ｃ）に示すように、絶縁
層２の側面にｌ’ｏｌｙ−８ｉ　４が残る。その後ＷＦ
６を用い減圧下でタングステン（５）５を形成し第３図
（ｄ）のごとくするっその後第３図（ｅ）に示すように
、例えば厚さ１．０μｍのｋｌ−８ｉ模６を蒸着し、写
真蝕刻法によって形成されたレジスト膜をマスクにしＣ
Ｃ１４−Ｃ１２ガスによってエツチングを行ない、配線
層を形成した後、レジスト膜を除去し、素子表面を例え
ば５ｉＨ４−Ｎ２０ガスを用い厚さ１．０μｍ程度の酸
化膜７全形成し、素子保護膜とする。As shown in FIG. 3(a), a silicon dioxide film 2 with a thickness of, for example, ~1 μm is formed on a silicon substrate 1, a pattern of a photoresist film 3 is formed thereon by photolithography, and using this as a mask, a hydrofluoric acid film 2 is formed. Etching is performed using an aqueous solution or a CF4-H2 gas to form an insulating layer. After removing the photoresist film 3, as shown in FIG. 3(b), a PO1y-8i film 4 with a thickness of, for example, 0.5 μm is formed (7) and reactive ion etching is performed using BBr3-C12 gas. . Then, l'oly-8i 4 remains on the side surface of the insulating layer 2, as shown in FIG. 3(C). Then WF
6 is used to form tungsten (5) 5 under reduced pressure as shown in FIG. 3(d). Then, as shown in FIG. Then, using a resist film formed by photolithography as a mask, C
After forming a wiring layer by etching with C14-C12 gas, the resist film is removed, and an oxide film 7 with a thickness of about 1.0 μm is completely formed on the surface of the element using, for example, 5iH4-N20 gas to form an element protective film. do.

（６）発明の効果 このようにして得られたタングステン膜は、絶縁層側面
に残されたｐｏｌｙ−８ｉによって膜の成長が第２図（
Ｃ）に示すように三方向から同時に起こるため、膜の成
長が速く、しかも膜厚の均一性もよく今までタングステ
／膜形成の際問題とされていた膜の厚さの問題と、第１
図（Ａ）の部分のような膜厚の減少と形状、ひいてはこ
れによって起こる配線層の段切れを解決することができ
、集積度向上による配線層の段差を少なくし、配線層の
信頼性を高めることができる。(6) Effects of the invention In the tungsten film thus obtained, the growth of the film is inhibited by the poly-8i left on the side surface of the insulating layer (Fig. 2).
As shown in C), since the growth occurs simultaneously from three directions, the film grows quickly and the film thickness is uniform.
It is possible to solve the problem of the reduction in film thickness and shape as shown in Figure (A), and the breakage of the wiring layer caused by this, thereby reducing the difference in height of the wiring layer due to the increase in integration density, and improving the reliability of the wiring layer. can be increased.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体装置の製造方法における問題点を
説明する為の断面図、第２図（ａ）〜（Ｃ）は本発明の
基本構成を説明するだめの工程断面図、第３図（ａ）〜
（ｅ）は本発明の一実施例における半導体装置の製造工
程を示す断面図である。 ｌ　・シリコン基板、　　２　二酸化硅素膜、３・・フ
ォトレジスト、　　４・・・Ｐｏ１ｙ−８ｉ　。 ５・・タングステン、　６・・ｋｌ−８ｉ、７・・・酸
化膜（保護膜） 代理人　弁理士　　則　近　憲　佑 （ほか１名） （力 第１図 第２図 ２７５−FIG. 1 is a cross-sectional view for explaining problems in the conventional semiconductor device manufacturing method, FIGS. 2(a) to (C) are process cross-sectional views for explaining the basic structure of the present invention, and FIG. (a)～
(e) is a cross-sectional view showing a manufacturing process of a semiconductor device in an embodiment of the present invention. 1. Silicon substrate, 2. Silicon dioxide film, 3.. Photoresist, 4.. Po1y-8i. 5...Tungsten, 6...kl-8i, 7...Oxide film (protective film) Agent: Patent attorney Noriyuki Chika (and 1 other person) (Figure 1, Figure 2, 275-

Claims (4)

【特許請求の範囲】[Claims] （１）半導体基板上に、開孔部をもつ絶縁膜を形成する
工程と、この絶縁膜及び開孔部上に導体膜を形成する工
程と、その後エツチングにより開孔部絶縁膜側壁に導体
膜を残存せしめる工程と、この絶縁膜開孔部に選択的に
金属膜を埋め込む工程とを特徴とする半導体装置の製造
方法。(1) A step of forming an insulating film with an opening on a semiconductor substrate, a step of forming a conductive film on this insulating film and the opening, and then etching the conductive film on the side wall of the insulating film in the opening. 1. A method for manufacturing a semiconductor device, comprising: a step of causing the insulating film to remain; and a step of selectively embedding a metal film into the opening of the insulating film. （２）導体膜はシリコン、高融点金属及びその硅化物で
あることを特徴とする特許 １項記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to Patent No. 1, wherein the conductor film is made of silicon, a high melting point metal, or a silicide thereof. （３）エツチングは，反応性イオンエツチングであるこ
とを特徴とする前記特許請求の範囲．ｉ＠１項記載の半
導体装１ｔの製造方法。(3) The above-mentioned claim characterized in that the etching is reactive ion etching. i@ A method for manufacturing a semiconductor device 1t according to item 1. （４）金属膜の形成方法は、気相成長法であることを特
徴とする前記特許請求の範囲第１項記載の半導体装置の
製造方法。(4) The method for manufacturing a semiconductor device according to claim 1, wherein the method for forming the metal film is a vapor phase growth method.