JPS5891654A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5891654A
JPS5891654A JP56190229A JP19022981A JPS5891654A JP S5891654 A JPS5891654 A JP S5891654A JP 56190229 A JP56190229 A JP 56190229A JP 19022981 A JP19022981 A JP 19022981A JP S5891654 A JPS5891654 A JP S5891654A
Authority
JP
Japan
Prior art keywords
chip
bonding
area
holes
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56190229A
Other languages
English (en)
Inventor
Masayoshi Ogawa
正芳 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56190229A priority Critical patent/JPS5891654A/ja
Publication of JPS5891654A publication Critical patent/JPS5891654A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 この発明は半導体チップの裏面にボンディング領域を作
ることによりチップ面積の縮小を図る三次元ボンディン
グに関するものである。
従来、ボンディング領域は半導体チップの活性領域にあ
り、チップ面積を増大させていた。しかるにチップ面積
が増大すると歩留が悪くなるという関係がある。
この発明は上記の点に鑑みてなされたもので、半導体チ
ップの裏面にボンディング領域を作ることによりチップ
面積の縮小を図った半導体装置を提供するものである。
以下図示実施例により、この発、明の詳細について述べ
る。第１図はこの発明の一実施例を示す断面図であり、
（１）は活性領域、（２）は裏面、（３）は活性領域（
１）と裏面（２）にあるボンディング領域（４）とを電
気的につなぐ導体を示す。４２図はこの発明の活性領域
（１）と裏面（２）との接続過程を示す説明図である。
エツチングにより裏面から活性領域（１１へ穴を開け（
第２図ム）、裏面を酸化し穴の回りに酸化膜（５）を作
成する（第２図Ｂ）ｏ穴に導体（３）を入れ、その上に
ボンディング領域（４）を作成する（第２図０）ｏまた
、導体（３）にはんだを使用することにより厚膜基板（
例えばセラミック基板）に直接ボンディングしてもよい
。第３図は本発明による半導体チップ（７）と厚膜基板
（８）をバンプ（６）により接合した場合を示す図であ
る。接合方式は第３図のような７リツプチツプ方式たけ
士なく、ワイヤボンディング法も使用してもよい。
【図面の簡単な説明】
第１図はこの発明の一実施例を示す断面内である。第２
図ム〜０はこの発明の活性領域と裏面との接続過程を示
す説明図である。第３図は本発明による半導体チップを
厚膜基板に接合した場合の側面図である。 図中、（１）は活性領域、（２）は裏面、（３）は導体
、（４）はボンディング領域、（５）は酸化膜、（６）
はパンダ、（７）は半導体チップ、（８）は厚膜基板を
示す。 なお、各図中同一符号は同一または相当部分を示すもの
とする。 代理人為野信− 第１図 第２図 第１３図

Claims (1)

    【特許請求の範囲】
  1. 半導体チップの裏面にボンディング領域を有することを
    特徴とする半導体装置。
JP56190229A 1981-11-26 1981-11-26 半導体装置 Pending JPS5891654A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56190229A JPS5891654A (ja) 1981-11-26 1981-11-26 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56190229A JPS5891654A (ja) 1981-11-26 1981-11-26 半導体装置

Publications (1)

Publication Number Publication Date
JPS5891654A true JPS5891654A (ja) 1983-05-31

Family

ID=16254629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56190229A Pending JPS5891654A (ja) 1981-11-26 1981-11-26 半導体装置

Country Status (1)

Country Link
JP (1) JPS5891654A (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5336184A (en) * 1976-09-16 1978-04-04 Seiko Epson Corp Semiconductor integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5336184A (en) * 1976-09-16 1978-04-04 Seiko Epson Corp Semiconductor integrated circuit

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