JPS58440U - プラスチツクパツケ−ジ - Google Patents

プラスチツクパツケ−ジ

Info

Publication number
JPS58440U
JPS58440U JP9394681U JP9394681U JPS58440U JP S58440 U JPS58440 U JP S58440U JP 9394681 U JP9394681 U JP 9394681U JP 9394681 U JP9394681 U JP 9394681U JP S58440 U JPS58440 U JP S58440U
Authority
JP
Japan
Prior art keywords
plastic packaging
lead frame
plastic
die attach
plastic package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9394681U
Other languages
English (en)
Other versions
JPS6223097Y2 (ja
Inventor
薗　陸郎
英夫 鈴木
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP9394681U priority Critical patent/JPS58440U/ja
Publication of JPS58440U publication Critical patent/JPS58440U/ja
Application granted granted Critical
Publication of JPS6223097Y2 publication Critical patent/JPS6223097Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来技術にかかる半導体装置用プラスチックパ
ッケージの概念的平面図であり、第２図はそのＡ−Ａ断
面図である。第３図は本考案の一実施例に係る半導体装
置用プラスチックパッケージの、第２図に対応する面に
おける断面図である。 １・・・半導体装置素子、２，２′・・・リードフレー
ム、３・・・ダイアタッチ部、４・・・ピン１．５・・
・成形された樹脂部、６・・・クラック、７・・・軟質
樹脂層。

Claims (1)

    【実用新案登録請求の範囲】
  1. リードフレームに乗せられた素子が樹脂をもってモール
    ドされてなるプラスチックパッケージにおいて、前記リ
    ードフレームが前記素子を支持する前記リードフレーム
    のダイアタッチ部下面に形成された軟質樹脂層を有する
    ことを特徴と−する、プラスチックパッケージ。
JP9394681U 1981-06-25 1981-06-25 プラスチツクパツケ−ジ Granted JPS58440U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9394681U JPS58440U (ja) 1981-06-25 1981-06-25 プラスチツクパツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9394681U JPS58440U (ja) 1981-06-25 1981-06-25 プラスチツクパツケ−ジ

Publications (2)

Publication Number Publication Date
JPS58440U true JPS58440U (ja) 1983-01-05
JPS6223097Y2 JPS6223097Y2 (ja) 1987-06-12

Family

ID=29888902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9394681U Granted JPS58440U (ja) 1981-06-25 1981-06-25 プラスチツクパツケ−ジ

Country Status (1)

Country Link
JP (1) JPS58440U (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60164343A (ja) * 1984-02-06 1985-08-27 Nitto Electric Ind Co Ltd 半導体装置載置基板の製造方法
JPS636751U (ja) * 1986-06-30 1988-01-18
JPS63142855U (ja) * 1987-03-11 1988-09-20
JP2010500757A (ja) * 2006-08-11 2010-01-07 ヴィシャイ ジェネラル セミコンダクター エルエルシー 半導体装置及び半導体装置の製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS498596A (ja) * 1972-05-15 1974-01-25
JPS533011U (ja) * 1976-06-25 1978-01-12
JPS5461556U (ja) * 1977-10-07 1979-04-28

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS498596A (ja) * 1972-05-15 1974-01-25
JPS533011U (ja) * 1976-06-25 1978-01-12
JPS5461556U (ja) * 1977-10-07 1979-04-28

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60164343A (ja) * 1984-02-06 1985-08-27 Nitto Electric Ind Co Ltd 半導体装置載置基板の製造方法
JPS636751U (ja) * 1986-06-30 1988-01-18
JPS63142855U (ja) * 1987-03-11 1988-09-20
JP2010500757A (ja) * 2006-08-11 2010-01-07 ヴィシャイ ジェネラル セミコンダクター エルエルシー 半導体装置及び半導体装置の製造方法

Also Published As

Publication number Publication date
JPS6223097Y2 (ja) 1987-06-12

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