JPS583613U - clamp circuit - Google Patents
clamp circuitInfo
- Publication number
- JPS583613U JPS583613U JP9572581U JP9572581U JPS583613U JP S583613 U JPS583613 U JP S583613U JP 9572581 U JP9572581 U JP 9572581U JP 9572581 U JP9572581 U JP 9572581U JP S583613 U JPS583613 U JP S583613U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- bias voltage
- voltage source
- polarity
- clamp circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図及び第2図は従来のクランプ回路を説明するため
の接続図、第3図はこの考案の一実施例を示す接続図、
第4図はその動作を説明するためのグラフである。
1:反転増幅器、2:出力端子、5:電圧入力端子、5
′ :電流入力端子、15. 16:バイアス電圧発生
用トランジスタ、25. 26:クランプ用ダイオード
、19:バイアス電圧源、22. 23:設定電圧発生
手段。1 and 2 are connection diagrams for explaining a conventional clamp circuit, and FIG. 3 is a connection diagram showing an embodiment of this invention.
FIG. 4 is a graph for explaining the operation. 1: Inverting amplifier, 2: Output terminal, 5: Voltage input terminal, 5
': Current input terminal, 15. 16: Bias voltage generation transistor, 25. 26: Clamp diode, 19: Bias voltage source, 22. 23: Setting voltage generation means.
Claims (1)
れるトランジスタフ、このトランジスタがオンになって
いる状態においてエミッタ抵抗に発生する電圧によりオ
フに保持され一端が上記極性反転増幅器の入力端に接続
されたダイオードと、上記極性反転増幅器の出力を上記
バイアス電圧源の電圧に加算する手段とを具備し、上記
極性反転増幅器の出力が上記バイアス電圧源に設定した
設定電圧にはN゛等しくなったとき上記ダイオードが導
通しクランプ状態となるようにしたクランプ回路。A polarity inverting amplifier, a transistor held on by a bias voltage source, and a transistor held off by a voltage generated in the emitter resistance when the transistor is on, one end of which is connected to the input terminal of the polarity inversion amplifier. a diode, and means for adding the output of the polarity reversing amplifier to the voltage of the bias voltage source, when the output of the polarity reversing amplifier becomes equal to the set voltage set to the bias voltage source. A clamp circuit in which the above diode conducts and is in a clamped state.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9572581U JPS583613U (en) | 1981-06-26 | 1981-06-26 | clamp circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9572581U JPS583613U (en) | 1981-06-26 | 1981-06-26 | clamp circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS583613U true JPS583613U (en) | 1983-01-11 |
JPS6325775Y2 JPS6325775Y2 (en) | 1988-07-13 |
Family
ID=29890618
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9572581U Granted JPS583613U (en) | 1981-06-26 | 1981-06-26 | clamp circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS583613U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6310012U (en) * | 1986-07-07 | 1988-01-22 |
-
1981
- 1981-06-26 JP JP9572581U patent/JPS583613U/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6310012U (en) * | 1986-07-07 | 1988-01-22 |
Also Published As
Publication number | Publication date |
---|---|
JPS6325775Y2 (en) | 1988-07-13 |
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