JPS58200559A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58200559A
JPS58200559A JP57083142A JP8314282A JPS58200559A JP S58200559 A JPS58200559 A JP S58200559A JP 57083142 A JP57083142 A JP 57083142A JP 8314282 A JP8314282 A JP 8314282A JP S58200559 A JPS58200559 A JP S58200559A
Authority
JP
Japan
Prior art keywords
aluminum
resin
lead
semiconductor device
tab
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57083142A
Other languages
Japanese (ja)
Inventor
Hiromichi Suzuki
博通 鈴木
Kenichi Otsuka
大塚　憲一
Wahei Kitamura
北村　和平
Hajime Sato
佐藤　始
Hiroshi Mikino
三木野　博
Susumu Okikawa
進 沖川
Ryosuke Kimoto
良輔 木本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP57083142A priority Critical patent/JPS58200559A/en
Publication of JPS58200559A publication Critical patent/JPS58200559A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/83424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve adhesive property between a lead and a resin, and to enhance humidity-proof property and reliability while reducing cost by forming an aluminum layer to a contact interface with the resin of the lead. CONSTITUTION:The aluminum layers 4 are formed to the inner leads 3, a tab 2 and the surfaces of tab leads, and a semiconductor element pellet 5 is fixed to the tab 2. The aluminum layers 4 are formed through plating, evaporation or cladding or the like, and pure aluminum or an aluminum alloy is used. The so- called corrosion-risisting aluminum containing manganese of 0.1-5.0% or magnesium of the same % or titanium of the same % or the like may be used. Since the aluminum layers 4 interpose to the contact interface between the leads 1 and the resin 8, adhesive propety between the lead and the resin is improved by high adhesive property between aluninum and the resin, and the intrusion of moisture through the interface is prevented.

Description

【発明の詳細な説明】 本発明は１罠プラスチックパッケージにおける耐湿性の
向上を図った半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device with improved moisture resistance in a one-trap plastic package.

一般にプラスチックパッケージの半導体装置は、リード
フレーム上に半導体素子ベレットを固着した上でペレッ
トとリードとをワイヤにて接続し、しかる上でペレット
やワイヤをレジン等にて封止する構成としたものが多い
。ところで、この種の半導体装置ではペレットの熱膨張
率との関係等かう１３−１’フレームの材質に４２アロ
イ、コバール等の金属を使用しているが、これらの金属
はパッケージ用レジンとの密着性（濡れ性）が蒸機良好
ではなく、リードフレームとレジンとの界面を通してパ
ッケージ内部に湿気が浸入し易いものとなっている。こ
のような不具合は新開螢光探傷法で確認されているが、
このように内部に湿気が浸入するとワイヤやペレットに
好ましくない影ＱＹ与える。特に近年では低コスト化を
図ってワイヤＫＡ４線を使用しているためワイヤが腐蝕
され易く、また同様にしてＡＪ材からなるペレットの電
他パッドや配線が腐蝕され易く、半導体装置の耐湿性お
よび信頼性を低下する原因となっているうしたがって本
発明の目的は耐湿性およγド偏幀性を向上すると共に低
コスト化を図ることのできる半導体装置を提供すること
にある。Generally, semiconductor devices in plastic packages have a structure in which a semiconductor element pellet is fixed onto a lead frame, the pellet and the leads are connected with wires, and then the pellet and wires are sealed with resin or the like. many. By the way, in this type of semiconductor device, metals such as 42 alloy and Kovar are used as the material of the 13-1' frame due to the relationship with the thermal expansion coefficient of the pellet, but these metals have a relationship with the resin for the package. The wettability of the package is not good, and moisture easily infiltrates into the package through the interface between the lead frame and the resin. Such defects have been confirmed using the newly developed fluorescence flaw detection method,
If moisture intrudes into the interior in this way, it will give an unfavorable shadow QY to the wires and pellets. In particular, in recent years, KA4 wire has been used to reduce costs, so the wire is easily corroded. Similarly, the electrical pads and wiring of pellets made of AJ material are also easily corroded, and the moisture resistance of semiconductor devices has deteriorated. Therefore, it is an object of the present invention to provide a semiconductor device which can improve moisture resistance and γ-mode deviation, and can reduce costs.

以下、本発明を図示の実施例により説明する。Hereinafter, the present invention will be explained with reference to illustrated embodiments.

第１図は本発明の一実施例に従った半導体装置の断面図
である。同図において、１は例えば４２７０イ等の材料
にて形成されたリードである。２はタブ％　３はインナ
リードである。これらインナれており、タブ２には半導
体素子ペレット５が固着され、そのｔａパッドとインナ
リード３とはアルミニウム線からなるワイヤ６にて接続
されている。前記アルミニウム層４はめっき、蒸着或い
はクラッド等にて形成し、またペレット５は銀ベースト
やアルミニウム半田等のペレット固着剤７にてタブ上に
固着している。そして、このように構成した構体は、例
えばトランスファモールドによってペレット５．ワイヤ
ｉ、ｌ□６．インナリード３等を封止レジン８にてバッ
クージしているのである。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. In the figure, 1 is a lead made of a material such as 4270I. 2 is the tab% and 3 is the inner lead. A semiconductor element pellet 5 is fixed to the tab 2, and the ta pad and the inner lead 3 are connected by a wire 6 made of an aluminum wire. The aluminum layer 4 is formed by plating, vapor deposition, cladding, etc., and the pellets 5 are fixed onto the tab with a pellet fixing agent 7 such as silver base or aluminum solder. The structure configured in this way is then formed into pellets 5. by transfer molding, for example. Wire i, l□6. The inner leads 3 and the like are sealed with a sealing resin 8.

なお、第２図に、−辷記第１図の半導体装置に用いるリ
ードフレーム１２を示す。同図かられかるようにアルミ
ニウム層４は同図の斜線で示す範囲に形成さ′れる。ま
た、アルミニウム層４は純アルミニウムやアルミニウム
合金を使用する。又、０．１〜５．０％のマンｊンまた
は同％のマグネシウム或いは同％のチタン等を含有した
所ｌ耐蝕アルミニウムを使用してもよい。図中、９はタ
ブリードである。Incidentally, FIG. 2 shows the lead frame 12 used in the semiconductor device of FIG. 1. As can be seen from the figure, the aluminum layer 4 is formed in the shaded area in the figure. Moreover, the aluminum layer 4 uses pure aluminum or an aluminum alloy. Furthermore, corrosion-resistant aluminum containing 0.1 to 5.0% manganese, the same % magnesium, or the same % titanium may be used. In the figure, 9 is a tab lead.

以上の構成によれば、リード１とレジン８との接触界面
にアルミニウム層４が介在されているので、アルミニウ
ムとレジンとの高い密着性によってリードとレジンとの
密着性が向上し、両者の界面を通しての湿気のレジン内
部への浸入を防止する。したがって、アルミニウム層の
電極パッドの腐蝕を防止し得ると共に、ワイヤに金線よ
りも低価格のアルミニウム線を使用しても腐蝕の心配７
まなく、半導体装置の耐湿性および信頼性を向上しかつ
低コスト化を雫・盛する。また、リード１のインナリー
ド３にアルミニウム層を設けたことｖｃより、従来のよ
うに金めつぎ層を形成しなくとも１ツイヤ６を直接イン
ナリードに接続することがでさる。更に金めつき層或い
は銀めっき層または金ワイヤ′を使用しないので、従来
の部分的な金、銀による局部電池作用によるアルミニウ
ムの溶出を防Ｉ卜することもできる。According to the above configuration, since the aluminum layer 4 is interposed at the contact interface between the lead 1 and the resin 8, the adhesion between the lead and the resin is improved due to the high adhesion between the aluminum and the resin, and the interface between the two Prevents moisture from entering the resin through. Therefore, corrosion of the electrode pad of the aluminum layer can be prevented, and even if aluminum wire, which is cheaper than gold wire, is used for the wire, there is no risk of corrosion.
The aim is to improve the moisture resistance and reliability of semiconductor devices, and to reduce costs. Further, since the aluminum layer VC is provided on the inner lead 3 of the lead 1, the wire 6 can be directly connected to the inner lead without forming a gold plating layer as in the conventional case. Furthermore, since a gold plating layer, a silver plating layer, or a gold wire is not used, it is possible to prevent the elution of aluminum due to the conventional local battery action caused by partial gold and silver.

ここで、アルミニウム層４は主にワイヤ６およびその近
傍への湿気の浸入を防止するものであることから、第３
図に示すアルミニ９ム層４人のようにタブ２やインナリ
ード３等の上面にのみ設けるようＫしてもよい。また、
第４図のようＫ　１７−ド７レーム１２と・レジン８と
の界面の周囲部分、換言すればワイヤ６やペレット５を
包囲するようにしてインナリード３の近傍にのみアルミ
ニウム層４Ｂを設けてもよい。いずれＫしてもアルミニ
ウム層４Ａ、４Ｂを設けた部位におけるリードフレーム
とレジンとの密着性を向上し【該部位を通しての湿気の
浸入を有効に防止することができる。Here, since the aluminum layer 4 mainly prevents moisture from entering the wire 6 and its vicinity, the third
It may be provided only on the top surface of the tab 2, inner lead 3, etc., as shown in the figure with four aluminum 9-layer layers. Also,
As shown in FIG. 4, an aluminum layer 4B is provided only in the vicinity of the inner lead 3 so as to surround the interface between the K17 frame 12 and the resin 8, in other words, to surround the wire 6 and pellet 5. Good too. In any case, the adhesion between the lead frame and the resin is improved in the areas where the aluminum layers 4A and 4B are provided, and the infiltration of moisture through the areas can be effectively prevented.

上記した半導体装置におい、て、リードと回路基板との
接続を容易にするためＫ、又はリードの腐蝕を防止する
ために封止レジン８から突出するＩ７−ド（アウターリ
ード）表面に半田を被覆する。In the semiconductor device described above, solder is coated on the surface of the I7-do (outer lead) protruding from the sealing resin 8 to facilitate the connection between the lead and the circuit board, or to prevent corrosion of the lead. do.

第５図は本発明の他の実施例に従った半導体装置の断面
図を示すものである。この実施例は特にアウターリード
に半田コートを施すタイプの半導体装置に有効である。FIG. 5 shows a cross-sectional view of a semiconductor device according to another embodiment of the invention. This embodiment is particularly effective for a type of semiconductor device in which the outer leads are coated with solder.

同図に示すように、リード１のインナーリード３．タブ
２、表面にアルミニウム層４が形成され、上記タブ２上
に銀ペースト又はアルミニウム半田等のベレット同系剤
７に℃半導体ベレット５が固着されている。上記半導体
ペレット７表面の電極パッドとインナーリード３とはア
ルミニ９ム線からなるワイヤ６にて接続されている。そ
して、上記半導体ペレット５．タブ２、インナーリード
３．ワイヤ６を封止レジン８で封止している。さらに、
上記リード１のアウターリード１０表面に半田層１１が
形成されている。As shown in the figure, inner lead 3 of lead 1. An aluminum layer 4 is formed on the surface of the tab 2, and a °C semiconductor pellet 5 is fixed onto the tab 2 with a pellet-like agent 7 such as silver paste or aluminum solder. The electrode pad on the surface of the semiconductor pellet 7 and the inner lead 3 are connected by a wire 6 made of aluminum 9mm wire. And the semiconductor pellet 5. Tab 2, inner lead 3. The wire 6 is sealed with a sealing resin 8. moreover,
A solder layer 11 is formed on the surface of the outer lead 10 of the lead 1.

この半田層１１は封止レジン８で榎われるイイナ−１１
−ド３表面にまで延在している。言い換えるならば、中
圧層１１が封止レジン８内部に食い込んで形成されてい
る。This solder layer 11 is covered with a sealing resin 8.
- Extends to the surface of the board 3. In other words, the intermediate pressure layer 11 is formed by cutting into the interior of the sealing resin 8.

このようＫして構成された半導体装置は、半田層１１が
レジン８内部に食い込んで形成されるので、レジンモー
ルド時、レジンパリが生じ、その後このパリがはがれて
もリード表面は半田層でコートされているためリードの
腐蝕が防止される。In the semiconductor device constructed in this way, the solder layer 11 is formed by digging into the inside of the resin 8, so even if resin patter occurs during resin molding and the pall peels off afterwards, the lead surface will not be coated with the solder layer. This prevents lead corrosion.

レジンでモールド後、封止レジンから突出しているリー
ド（アウターリード）表面のみに半田コートしたのでは
、上記モールド時レジンバリが生じた場合このパリがは
がれると、このパリ下の半田コートされていないリード
表面が外部１Ｃｊｃ出してしまう。従って、この露出し
たリード（半田コートされていない部分）から腐蝕が生
じてしまう。After molding with resin, if only the surfaces of the leads (outer leads) protruding from the sealing resin are coated with solder, if resin burrs occur during the above molding process and these burrs are peeled off, the unsolder-coated leads under these burrs will be removed. The surface exposes 1Cjc to the outside. Therefore, corrosion occurs from these exposed leads (portions not coated with solder).

さらに、第５図に示した半導体装置においては。Furthermore, in the semiconductor device shown in FIG.

半田層１１は封止レジン８との境界部処おいても均一な
半田厚さが得られるので、従来のように封止レジン周囲
部におけるレジンバリによる半田付着不良（半田層の厚
さが不足するためにアウタリードの曲げ時に応力集中を
生じてアウタリードが根本から折れ易くなる）が男、、
ｌじることもない。Since the solder layer 11 has a uniform solder thickness even at the boundary with the sealing resin 8, it is possible to prevent poor solder adhesion (insufficient solder layer thickness) due to resin burrs around the sealing resin, as in the past. (This causes stress concentration when bending the outer lead, making it easier for the outer lead to break from the root.)
Never give up.

第６図は第５図に示した半導体装置の製法の一例を示す
断面図である。まず同図（Ａ）Ｋ示すようにリード１．
タブ２．インナリード３はもとより、アウタリード１０
を含む全表面にわたってアルミニウム層４な形成し、そ
の上でペレット５の固着、アルミニウム線によるワイヤ
６の接続および封止レジン８によるパッケージを完成す
る。その後、同図（ハ）のようにアルミニウムのエツチ
ング剤を用いてアクタリード表面に形成されたアルミニ
ウム層なエツチング除去する。このとぎ、若干オーバエ
ツチングを行なうことにより同図のように封止レジン８
の内部に食い込んでアルミニウム層４がエツチングされ
るようにする。そして、その後に同図（ｑのようにアウ
タリード１００表面に半田をコートして半田１１１を形
成し、半導体装置を完成するのである。FIG. 6 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. First, lead 1.
Tab 2. Inner lead 3 as well as outer lead 10
An aluminum layer 4 is formed over the entire surface including the aluminum layer 4, and a pellet 5 is fixed thereon, a wire 6 is connected using an aluminum wire, and a package is completed using a sealing resin 8. Thereafter, as shown in FIG. 3C, the aluminum layer formed on the surface of the ActaLead is etched away using an aluminum etching agent. After this, by slightly overetching the sealing resin 8 as shown in the same figure.
The aluminum layer 4 is etched by cutting into the inside of the aluminum layer 4. Thereafter, the surface of the outer lead 100 is coated with solder to form solder 111 as shown in FIG.

のものでも本発明を閾様に適用できることは首う１″′
″′ｔｘｙ’ｏ　　　、＜３、 以上のような本発明によれば、リードのレジンとの接触
界面にアルミニウム層を形成（７ているので、アルミニ
ウムとレジンとの高密着力！、・こよ−）てリードとレ
ジンとの密着性が向上し、これ罠よりアルミニウムのワ
イヤや電極パッド等の腐蝕を防止して耐湿性および信頼
性を向上しかつ装置の低コスト化を達成することができ
る、という効果を奏第１図は本発明の一実施例に従った
半導体装置の断面図。There is no doubt that the present invention can be applied in a threshold manner to
According to the present invention as described above, an aluminum layer is formed at the contact interface of the lead with the resin (7), so the adhesion between the aluminum and the resin is high! This improves the adhesion between the leads and the resin, which prevents corrosion of aluminum wires and electrode pads, improves moisture resistance and reliability, and lowers device costs. FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

第２図は第１図に示す半導体装置に用いられるリードフ
レームの平面図、 第３図は本発明の他の実施例に従った半導体装置の断面
図、 第４図は本発明の変形例のリードフレームの平面図、 第５図は本発明の他の実施例に従った半導体装置の断面
図、 ＃Ｉ６図四〜（Ｃ１は第５図に示した半導体装置の製造
方法の一例を示す工程断面図である。2 is a plan view of a lead frame used in the semiconductor device shown in FIG. 1, FIG. 3 is a sectional view of a semiconductor device according to another embodiment of the invention, and FIG. A plan view of a lead frame; FIG. 5 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention; #I6 FIGS. FIG.

１・・・リード、２・・・タブ、３・・・インナリード
、４゜４Ａ、４Ｂ・・アルミニウム層、５・・・ペレッ
ト、６・・・ワイヤ、８・・・レジン、９・・・タブリ
ード、１０・・・アクタリード、１１・・・半田層、１
２・・・リードフレーム。DESCRIPTION OF SYMBOLS 1... Lead, 2... Tab, 3... Inner lead, 4° 4A, 4B... Aluminum layer, 5... Pellet, 6... Wire, 8... Resin, 9...・Tab lead, 10...Actor lead, 11...Solder layer, 1
2...Lead frame.

代理人　弁理士　　薄　１）利　幸 第　　１　　図 第　　２　図 ４　　　ｊ　　　　　　特開５８ 第　　３　　　ＩＮ 第　　４　　図 第　　５　　図 第　　６　　図 第１頁の続き ０発　明　者　木本良輔 小平市上水本町１４７９番地日立マ イクロコンピュータエンジニア リング株式会社内 ■出　願　人　日立マイクロコンピュータエンジニアリ
ング株式会社 小平市上水本町１４７９番地 ２６１−Agent Patent Attorney Susuki 1) Yukihiro Toshi 1 Figure 2 Figure 4 j JP-A-58-3 IN Figure 4 Figure 5 Figure 6 Continuation of Figure 1 Page 0 Inventor Ryosuke Kimoto 1479 Kamisui Honmachi, Kodaira City Address Hitachi Microcomputer Engineering Co., Ltd. ■Applicant Hitachi Microcomputer Engineering Co., Ltd. 1479-261, Josui Honmachi, Kodaira City

Claims (1)

【特許請求の範囲】 １、リードに半導体素子ペレットを固着しかつワイヤ接
続した状態でこれをレジンにて封止してなる半導体装置
において、前記リードはレジンとの接触界面部位にアル
ミニウム層を形成してなることを特徴とする半導体装置
。 ２、上記アルミニウム層はアルミニウム若しくはアルミ
ニウム合金を蒸着、めっき或いはクラッドにて膜状に形
成してなる特許請求の範囲第１項記載の半導体装置。 ３、上記アルミニウム層は少なくともペレットやワイヤ
を包囲する部分に形成してなる特許請求の範囲第１項又
は＃！２項記載の半導体装置。[Claims] 1. In a semiconductor device in which a semiconductor element pellet is fixed to a lead and sealed with a resin while connected with a wire, the lead has an aluminum layer formed at the contact interface with the resin. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the aluminum layer is formed into a film by vapor deposition, plating, or cladding of aluminum or an aluminum alloy. 3. The aluminum layer is formed at least in a portion surrounding the pellet or wire. The semiconductor device according to item 2.
JP57083142A 1982-05-19 1982-05-19 Semiconductor device Pending JPS58200559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57083142A JPS58200559A (en) 1982-05-19 1982-05-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57083142A JPS58200559A (en) 1982-05-19 1982-05-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58200559A true JPS58200559A (en) 1983-11-22

Family

ID=13793955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57083142A Pending JPS58200559A (en) 1982-05-19 1982-05-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58200559A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01160071A (en) * 1987-12-16 1989-06-22 Matsushita Electric Ind Co Ltd Laser oscillator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01160071A (en) * 1987-12-16 1989-06-22 Matsushita Electric Ind Co Ltd Laser oscillator

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