JPH03154344A - Resin-sealed semiconductor element - Google Patents
Resin-sealed semiconductor elementInfo
- Publication number
- JPH03154344A JPH03154344A JP1294371A JP29437189A JPH03154344A JP H03154344 A JPH03154344 A JP H03154344A JP 1294371 A JP1294371 A JP 1294371A JP 29437189 A JP29437189 A JP 29437189A JP H03154344 A JPH03154344 A JP H03154344A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor element
- mainframe
- sealed
- sealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 239000011347 resin Substances 0.000 claims abstract description 29
- 229920005989 resin Polymers 0.000 claims abstract description 29
- 238000007789 sealing Methods 0.000 claims abstract description 15
- 238000004806 packaging method and process Methods 0.000 abstract description 4
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- KCXVZYZYPLLWCC-UHFFFAOYSA-N EDTA Chemical compound OC(=O)CN(CC(O)=O)CCN(CC(O)=O)CC(O)=O KCXVZYZYPLLWCC-UHFFFAOYSA-N 0.000 description 1
- 101100229738 Mus musculus Gpank1 gene Proteins 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は樹脂封止型半導体素子に係り、特に回路基板に
搭載・実装して使用される樹脂封止された小型の半導体
素子に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a resin-sealed semiconductor device, and particularly to a small resin-sealed semiconductor device that is mounted and mounted on a circuit board. Related to semiconductor devices.
（従来の技術）
近年、電子機器においては小形化ないし高機能化が要求
されており、この要求に対応して半導体素子も高集積化
されている。また、この高集積化された半導体素子を所
要の回路基板上に、高密度に搭載・実装して使用する要
求ないし形態が増加している。(Prior Art) In recent years, there has been a demand for smaller size and higher functionality in electronic devices, and in response to this demand, semiconductor elements have also become highly integrated. In addition, there is an increasing demand for and use of highly integrated semiconductor elements mounted and mounted at high density on a required circuit board.
ところで、半導体素子を回路基板上に搭載・実装する手
段としては、挿入型のＤＩＰや表面実装型のＳＯＪなど
のように、パッケージ化された半導体素子をたとえばリ
フロー法により、回路基板上に半田付けする手段が知ら
れている。By the way, as a means to mount and mount a semiconductor element on a circuit board, a packaged semiconductor element such as an insertion type DIP or a surface mount type SOJ is soldered onto a circuit board using a reflow method. There are known ways to do this.
しかしながら、上記パッケージを用いる手段は、インナ
ーリードを含むパッケージサイズが半導体素子本体の３
〜４倍程度となり、高密度化に限界があった。この対策
として、パッケージ化せずに、ペアチップを回路基板上
に直接ダイマウントし、ボンディングワイヤでペアチッ
プのボンディングパッドと回路基板上のパッドとを接続
するＣ０Ｂ（チップオンボード）技術が高密度実装に採
用されるようになってきた。However, in the method using the above package, the package size including the inner leads is 3 times larger than the semiconductor element body.
It was about 4 times as large, and there was a limit to increasing the density. As a countermeasure to this problem, C0B (chip-on-board) technology, in which paired chips are die-mounted directly onto the circuit board without packaging and the bonding pads of the paired chips and pads on the circuit board are connected using bonding wires, is used to achieve high-density mounting. It is starting to be adopted.
しかして、上記ＣＯＢ技術では、高温高湿度に対する信
頼性保持のため、半導体素子本体の表面をボッティング
樹脂で被覆封止する方法が用いられていることが多い。However, in the above COB technology, in order to maintain reliability against high temperature and high humidity, a method is often used in which the surface of the semiconductor element body is coated and sealed with a botting resin.
しかし、樹脂のボッティングにより被覆封止する手段を
用いた構造は、チップないし素子本体とこれを搭載する
回路基板、さらに被覆するボッティング樹脂と各々の熱
膨張係数が最大１桁と相異する場合が多いため、温度サ
イクルが機器に加わった場合は素子本体を中心としてク
ラックが生じたり、ワイヤーがはずれたりして信頼性上
問題があるばかりでなく、ボンディングワイヤーを含め
た接続に必要とされる面積も素子本体の２〜３倍必要と
なり、高密度実装の上で問題がある。However, in a structure using resin botting to cover and seal, the coefficient of thermal expansion of the chip or element body, the circuit board on which it is mounted, and the covering botting resin differs by up to an order of magnitude. Therefore, if temperature cycles are applied to the device, not only will cracks occur around the device body and wires may come off, causing problems with reliability, but also the The area required is two to three times that of the element body, which poses a problem in high-density packaging.
これらの問題に対してバンプ電極を介して基板上にフェ
イスダウンで接続するフリップチップ実装が近年注目を
浴びている。この手段は予め回路パターンが形成された
回路基板上に、バンプ電極を介して半導体素子本体をフ
ェイスダウンで実装することから、その実装密度もチッ
プ面積と同等にでき高密度化が可能となる。In response to these problems, flip-chip mounting, which connects devices face-down onto a substrate via bump electrodes, has been attracting attention in recent years. Since this means mounts the semiconductor element body face-down via bump electrodes on a circuit board on which a circuit pattern has been formed in advance, the mounting density can be made equal to the chip area and high density can be achieved.
（発明が解決しようとする課題）
しかしながら、上記バンプ電極を介して半導体素子本体
をフェイスダウンで実装する手段は、ペアチップを実装
するため、樹脂をボッティングし被覆封止しない場合バ
ンプ電極を介した隙間から水分の浸入が起こり耐湿上問
題が起きる。一方、樹脂をボッティングまたは回路基板
をペアチップ間に挿入した場合は、先に述べたような熱
膨張係数の相異が熱的ストレスの影響を受は易く高信頼
性を保持できないという不都合がある。さらに、実装段
階においてペアチップを取り扱うことから温度、湿度、
保存雰囲気など保存環境の維持にコストがかかるばかり
でなく、チッピングなどの不良が発生する割合も高いと
いう問題がある。(Problem to be Solved by the Invention) However, the means for face-down mounting of the semiconductor element body through the bump electrodes described above is difficult to mount through the bump electrodes when the resin is not potted and sealed to mount a pair of chips. Moisture can enter through the gaps, causing moisture resistance problems. On the other hand, when resin is botted or a circuit board is inserted between a pair of chips, there is the disadvantage that the difference in thermal expansion coefficients mentioned above is easily affected by thermal stress and high reliability cannot be maintained. . Furthermore, since paired chips are handled during the mounting stage, temperature, humidity,
There is a problem in that not only is it costly to maintain a storage environment such as a storage atmosphere, but also the rate of defects such as chipping is high.
本発明は上記問題に鑑みてなされたもので、高密度実装
が可能でかつ、取扱いの容易な信頼性ある樹脂封止型半
導体素子を提供するものである。The present invention has been made in view of the above problems, and it is an object of the present invention to provide a reliable resin-sealed semiconductor element that can be mounted at high density, is easy to handle, and is easy to handle.
［発明の構成］
（課題を解決するための手段）
本発明は、回路基板の所定領域面に搭載・実装される樹
脂封止型半導体素子であって、前記回路基板のボンディ
ングパッドに対応するバンプ電極が半導体素子本体を被
覆封止する樹脂層の少なくとも一主面上に形設されて成
ることを特徴とする。[Structure of the Invention] (Means for Solving the Problems) The present invention provides a resin-sealed semiconductor element mounted and mounted on a predetermined area surface of a circuit board, the semiconductor element having bumps corresponding to bonding pads of the circuit board. It is characterized in that the electrode is formed on at least one main surface of a resin layer that covers and seals the semiconductor element body.
（作 用）
本発明によれば、外部端子としてのバンプ電極を有する
樹脂封止層（パッケージ）を具備するため、パッケージ
自体の小型化が可能となる。また、フリップチップ実装
時にペアチップを用いた場合よりも耐湿性が向上し、信
頼性の向上を図り得るばかりでなく、半導体素子本体が
樹脂で被覆封止されているので取扱いも容易となる。加
えて、樹脂封止型半導体素子はダイパッドを有さない構
造であるため、水分の浸入に起因するりフロー時のクラ
ックが生じないという作用効果も同時に呈する。(Function) According to the present invention, since a resin sealing layer (package) having bump electrodes as external terminals is provided, the package itself can be miniaturized. In addition, moisture resistance is improved compared to when paired chips are used during flip-chip mounting, which not only improves reliability but also facilitates handling because the semiconductor element body is coated and sealed with resin. In addition, since the resin-sealed semiconductor element has a structure that does not have a die pad, it also exhibits the effect that cracks do not occur during flow due to moisture intrusion.
（実施例）
以下第１図を参照して本発明の詳細な説明する。第１図
は本発明に係る樹脂封止型半導体素子の構造例を示す断
面図で、１は樹脂封止型半導体素子、２は前記樹脂封止
型半導体素子の主要部を成す半導体素子本体、３ ａ
ｓ ３ ｂは前記半導体素子本体２を被覆封止する樹脂
層（パーツケージ本体）で、３ａはたとえば着色剤とし
てのカーボンなど適当なフィラーをを混入したエポキシ
樹脂また３ｂはたとえばα線速へいに用いる不純物濃度
をｐｐｍレベルに抑えたポリイミド樹脂でそれぞ形成さ
れている。さらに、４は前記半導体素子本体２の一生面
に形設されたＡＪ２ボンディングパッド、５は前記Ａｉ
ボンディングバット４と電気的に接続しているバンプ電
極たとえばＰｂ／Ｓｎ：９５１５のハンダ層である。(Example) The present invention will be described in detail below with reference to FIG. FIG. 1 is a cross-sectional view showing an example of the structure of a resin-sealed semiconductor element according to the present invention, in which 1 is a resin-sealed semiconductor element, 2 is a semiconductor element body forming the main part of the resin-sealed semiconductor element; 3 a
s 3 b is a resin layer (parts cage body) that covers and seals the semiconductor element body 2; 3 a is an epoxy resin mixed with a suitable filler such as carbon as a coloring agent; Each of them is made of polyimide resin with impurity concentration suppressed to ppm level. Furthermore, 4 is an AJ2 bonding pad formed on the entire surface of the semiconductor element body 2, and 5 is the AJ2 bonding pad formed on the entire surface of the semiconductor element body 2;
The bump electrode electrically connected to the bonding bat 4 is a solder layer of Pb/Sn:9515, for example.
次に上記構造の樹脂封止型半導体素子の製造例を説明す
る。先ず、前記半導体素子本体２を被覆封止する前に、
前記ハンダバンプ電極５を形成しする。すなわち、ポリ
イミド樹脂などからなる樹脂層３ｂを、へβボンディン
グパッド４部を除いて形成したウェハー上にＴｉ／Ｎｉ
／Ｃｕ薄膜を蒸着により１０００人／ ３０００人／
５０００人形成した上に、所要のバンプを形成する部分
にエツチングレジストを被覆し、Ｃｕ、Ｎｉ、Ｔｉを順
次エッチングする。このエツチングは、Ｃｕを過硫酸ア
ンモニウム水溶液により、Ｎｉはメタノール、塩酸、硫
酸銅の混合液により、Ｔｉはアンモニア、過酸化水素水
、エチレンジアミン四酢酸からなる混合液によるウェッ
トエツチングで行ない得る。かくして、Ａでボンディン
グパッド４に接続するＴｉ／Ｎ Ｌ ／ Ｃｕ接続パッ
ドを形成し、Ｓ ｎ ／ Ｐ ｂのハンダ槽内にデイツ
プすることでハンダ電極バンプを形成する。バンプを形
成後ウェハーをダイシングして半導体ベレット（半導体
素子本体）とする。Next, an example of manufacturing a resin-sealed semiconductor element having the above structure will be described. First, before covering and sealing the semiconductor element body 2,
The solder bump electrode 5 is formed. That is, a Ti/Ni film is deposited on a wafer on which a resin layer 3b made of polyimide resin or the like is formed except for 4 β bonding pads.
/ 1000 people / 3000 people / by vapor deposition of Cu thin film
After forming 5,000 bumps, an etching resist is coated on the portion where the desired bumps are to be formed, and Cu, Ni, and Ti are sequentially etched. This etching can be performed by wet etching Cu with an aqueous ammonium persulfate solution, Ni with a mixed solution of methanol, hydrochloric acid, and copper sulfate, and Ti with a mixed solution of ammonia, hydrogen peroxide, and ethylenediaminetetraacetic acid. In this way, a Ti/N L /Cu connection pad is formed to connect to the bonding pad 4 at A, and a solder electrode bump is formed by dipping it into a S n /P b solder bath. After forming the bumps, the wafer is diced into semiconductor pellets (semiconductor element bodies).
上記バンプ電極５が形成された半導体素子本体２を、た
とえば第２図にて断面的に示す構造の金型６内に配置し
、トランスファーモールドする。The semiconductor element body 2 on which the bump electrodes 5 are formed is placed, for example, in a mold 6 having a structure shown in cross section in FIG. 2, and transfer molded.
このモールド時の温度は、前記半導体素子本体２に形成
されたバンプ電極４であるハンダの融点以下で行い、被
覆封止樹脂層３ａは半導体素子本体２の厚さ以内で形成
されるように金型６の設計を行い、半導体素子本体２を
配置する。The temperature during this molding is below the melting point of the solder which is the bump electrode 4 formed on the semiconductor element body 2, and the coating sealing resin layer 3a is made of gold so that it is formed within the thickness of the semiconductor element body 2. A mold 6 is designed and the semiconductor element body 2 is placed.
上記により半導体素子本体２を樹脂封止して構成した樹
脂封止型半導体素子１は、被覆封止樹脂層３ｂ表面に対
してバンプ電極４が３０ｐ１±１０μｍ突出した形で形
成されており、また被覆封止樹脂層３ｂは５μｍの厚さ
で、被覆封止樹脂層３ａは半導体素子本体２の周囲を２
５０μｍの厚さで夫々被覆封止した構成を成していた。The resin-sealed semiconductor element 1 configured by resin-sealing the semiconductor element body 2 as described above is formed in such a manner that the bump electrodes 4 protrude by 30p1±10 μm from the surface of the covering sealing resin layer 3b. The covering sealing resin layer 3b has a thickness of 5 μm, and the covering sealing resin layer 3a surrounds the semiconductor element body 2 by 2 μm.
Each was coated and sealed with a thickness of 50 μm.
上記構成した樹脂封止型半導体素子１を８５℃、８５％
の高温高湿中に１０００）１放置したところ、特性は故
障判定基準に対してマージンをもって動作しており、腐
食などの不良は発生しなかった。The resin-sealed semiconductor element 1 having the above structure was heated to 85°C and 85%
When the device was left in a high temperature and high humidity environment of 1000)1, the characteristics operated with a margin against the failure criteria, and no defects such as corrosion occurred.
さらにこの樹脂封止型半導体素子１をセラミック基板上
にフリップチップ接続したところＪＩＳ ０７０２２
Ｊ：定める温度サイクル試験−５５℃（３０分）〜２５
℃（５分）〜１５０℃（３０分）〜２５℃（５分） ３
００ ｅｙｅ！ｅに対して断線などの不良発生もなく高
信頼性を有していることを確認した。また取扱い上の原
因で発生する不良もペアチップを取り扱う場合と比較し
て１０％減少させることができた。Furthermore, when this resin-sealed semiconductor element 1 was flip-chip connected to a ceramic substrate, it met JIS 07022.
J: Specified temperature cycle test -55℃ (30 minutes) ~ 25
℃ (5 minutes) ~ 150℃ (30 minutes) ~ 25℃ (5 minutes) 3
00 eye! It was confirmed that there was no occurrence of defects such as wire breakage, and that the wire had high reliability. Furthermore, the number of defects caused by handling was reduced by 10% compared to when handling paired chips.
本発明は上記実施例に限定されるものではなくその要旨
を逸脱しない範囲で種々変更可能である。The present invention is not limited to the above-described embodiments, and can be modified in various ways without departing from the gist thereof.
たとえば接続バンプの形成にＴ ｉ ｉ Ｎ ｉ ／
Ｃｕの代わりに、Ｔ ｉ ／ Ｎ ｉもしくはＴ ｉ
／ Ｎ ｉ ／ Ｐ ｄ／ Ａ ｕを用いてもよいし、
ハンダバンプ電極はＰｂ／５ｎ−９５１５に限られるも
のではなく、その形成方法は半導体素子本体２を樹ｆｆ
Ｗ３ａ、３ｂによって被覆した後に形成してもよい。さ
らにバンプ電極５はＡｕボンディングパッド４上に対応
して形成されるものに限らず、薄膜配線を引きまわし、
被覆封止樹脂層３ａの全面にわたって形成されるもので
あってもよい。For example, when forming connection bumps, T i i N i /
Instead of Cu, T i / N i or T i
/Ni/Pd/Au may be used,
The solder bump electrode is not limited to Pb/5n-9515, and the method for forming it is to
It may be formed after being coated with W3a and 3b. Furthermore, the bump electrodes 5 are not limited to those formed correspondingly on the Au bonding pads 4, but can also be formed by routing thin film wiring,
It may be formed over the entire surface of the covering sealing resin layer 3a.
［発明の効果］
本発明によれば、半導体素子本体の周囲を樹脂により薄
く被覆封止し、この被覆封止樹脂層からバンプ電極を露
出させ、これを外部接続端子としているために小型化が
可能となる。さらに、樹脂層で半導体素子本体を被覆封
止しであるため、フリップチップ実装時にペアチップを
用いた場合よりも耐湿性が大幅に向上するばかりでなく
、樹脂を基板上の半導体ベレットに対してポツティング
する場合と比較して熱的ストレスに対する耐性も向上す
る。また樹脂層で半導体素子本体を被覆封止しであるた
め、取扱いが容易となると同時にダイパッドを有さない
構造であるため水分の浸入に起因するりフロー時のクラ
ックが生じないという効果も生じる。[Effects of the Invention] According to the present invention, the periphery of the semiconductor element main body is thinly coated and sealed with a resin, and the bump electrodes are exposed from this coating and sealing resin layer and are used as external connection terminals, thereby achieving miniaturization. It becomes possible. Furthermore, since the semiconductor element body is covered and sealed with a resin layer, not only is moisture resistance significantly improved compared to when paired chips are used during flip-chip mounting, but also the resin can be potted onto the semiconductor pellet on the board. The resistance to thermal stress is also improved compared to the case where the Furthermore, since the semiconductor element body is covered and sealed with a resin layer, it is easy to handle, and at the same time, since the structure does not have a die pad, there is an effect that cracks do not occur during flow due to moisture intrusion.
第１図は本発明に係る樹脂封止型半導体素子の一構成例
を示す断面図、第２図は本発明に係る樹脂封止型半導体
素子の製造例を模式的に示す断面図である。
１・・・・・・・・・樹脂封止型半導体素子２・・・・
・・・・・半導体素子本体
３ａ、３ｂ・・・被覆封止する樹脂層
４・・・・・・・・・Ａβボンディングパッド５・・・
・・・・・・バンプ電極
６・・・・・・・・・モールド金型FIG. 1 is a cross-sectional view showing an example of the structure of a resin-sealed semiconductor element according to the present invention, and FIG. 2 is a cross-sectional view schematically showing an example of manufacturing the resin-sealed semiconductor element according to the present invention. 1...Resin-sealed semiconductor element 2...
...Semiconductor element bodies 3a, 3b...Resin layer 4 for coating and sealing...Aβ bonding pad 5...
・・・・・・Bump electrode 6・・・・・・Mold mold
Claims (1)
導体素子であって、 前記回路基板のボンディングパッドに対応するバンプ電
極が半導体素子本体を封止する樹脂層の少なくとも一主
面上に形設されて成ることを特徴とする樹脂封止型半導
体素子。[Scope of claims] A resin-sealed semiconductor element mounted/mounted on a predetermined area surface of a circuit board, wherein bump electrodes corresponding to bonding pads of the circuit board are connected to a resin layer sealing the semiconductor element body. 1. A resin-sealed semiconductor element formed on at least one principal surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1294371A JP2892055B2 (en) | 1989-11-13 | 1989-11-13 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1294371A JP2892055B2 (en) | 1989-11-13 | 1989-11-13 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03154344A true JPH03154344A (en) | 1991-07-02 |
| JP2892055B2 JP2892055B2 (en) | 1999-05-17 |
Family
ID=17806850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1294371A Expired - Fee Related JP2892055B2 (en) | 1989-11-13 | 1989-11-13 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2892055B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582582A (en) * | 1991-09-24 | 1993-04-02 | Nec Yamagata Ltd | Semiconductor device |
| US5710062A (en) * | 1993-06-01 | 1998-01-20 | Mitsubishi Denki Kabushiki Kaisha | Plastic molded semiconductor package and method of manufacturing the same |
| US5766972A (en) * | 1994-06-02 | 1998-06-16 | Mitsubishi Denki Kabushiki Kaisha | Method of making resin encapsulated semiconductor device with bump electrodes |
-
1989
- 1989-11-13 JP JP1294371A patent/JP2892055B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582582A (en) * | 1991-09-24 | 1993-04-02 | Nec Yamagata Ltd | Semiconductor device |
| US5710062A (en) * | 1993-06-01 | 1998-01-20 | Mitsubishi Denki Kabushiki Kaisha | Plastic molded semiconductor package and method of manufacturing the same |
| US5834340A (en) * | 1993-06-01 | 1998-11-10 | Mitsubishi Denki Kabushiki Kaisha | Plastic molded semiconductor package and method of manufacturing the same |
| US6046071A (en) * | 1993-06-01 | 2000-04-04 | Mitsubishi Denki Kabushiki Kaisha | Plastic molded semiconductor package and method of manufacturing the same |
| US5766972A (en) * | 1994-06-02 | 1998-06-16 | Mitsubishi Denki Kabushiki Kaisha | Method of making resin encapsulated semiconductor device with bump electrodes |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2892055B2 (en) | 1999-05-17 |
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