JPS5820028A - Code converter - Google Patents
Code converterInfo
- Publication number
- JPS5820028A JPS5820028A JP11814281A JP11814281A JPS5820028A JP S5820028 A JPS5820028 A JP S5820028A JP 11814281 A JP11814281 A JP 11814281A JP 11814281 A JP11814281 A JP 11814281A JP S5820028 A JPS5820028 A JP S5820028A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- reference potential
- converter
- decoder circuit
- capacitor array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はコンデンサアレイを用いた単−参照電位型符合
変換器即ち単−参照電位歴アナログディジタル変換器(
以下ムD変換器と称す)及び単−参照電位型ディジタル
アナログ変換器(以下DA変換器と称す)に係に参照電
位と接地電位を被変換信号の符号によ)切換える仁とに
よ〕デーーダ回路の簡単な符号変換器に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a single-reference potential type code converter, or a single-reference potential history analog-to-digital converter, using a capacitor array.
(hereinafter referred to as a digital-to-analog converter) and a single-reference potential type digital-to-analog converter (hereinafter referred to as a DA converter). Concerning a simple code converter circuit.
従来の単一参照電位WDA、ムDJR換器の例を第1図
第6図第6図第12図に示す0又動作原理の説明を第2
図〜第4図、第7図〜!11図に示す。図中1・、8社
デコーダ回路、2はバッファアンプ回路、3.10はコ
ンデンサアレイ、4.11はセレクタ回路、5.129
1正信号用デコード回路、6.13は負信号用デコード
回路、7は比較器、9.14は遂次比較レジスタ、C1
〜C3はコンデンサプレイの各コンデンサ、Cムはコン
デンサプレイの各コンデンサの総和、SW、〜8 Wn
はコンデンサアレイのスイッチ、SWG* 8WC*
8WDはスイッチ、■は参照電位、Voutはアナログ
出力、MINはアナ四グ入力、CX 、CYは参照電位
又は接地電位に接続され為コンデンサの和でCX+CY
−Cムである・最初にDA変換器の例で説明する0この
場合は正信号出力の場合と負信号出力の場合と動作モー
ドが分かれ、その中で又放電モードと出力モードとに分
かれる0正信号出力の放電モード及び負信号出力の放電
毫−ドをそれぞれ第2図、第411i1に示す0そして
出力峰−ドを第3図に示す0出力篭−ドは正信号の場合
と負信号の場合とが同様であるが出力電圧を示す;ンデ
ンサアレイ30−ンデンナの構成が異る◎正信号の場合
の出か電圧は次式(1)K示す°如くなる。An example of a conventional single reference potential WDA/MU DJR converter is shown in FIG. 1, FIG. 6, FIG. 6, and FIG. 12.
Figure ~Figure 4, Figure 7~! It is shown in Figure 11. In the figure, 1., 8 decoder circuit, 2 buffer amplifier circuit, 3.10 capacitor array, 4.11 selector circuit, 5.129
1 a decoding circuit for positive signals, 6.13 a decoding circuit for negative signals, 7 a comparator, 9.14 a sequential comparison register, C1
~C3 is each capacitor of the capacitor play, Cum is the sum of each capacitor of the capacitor play, SW, ~8 Wn
is a capacitor array switch, SWG* 8WC*
8WD is a switch, ■ is a reference potential, Vout is an analog output, MIN is an analog input, CX and CY are connected to a reference potential or ground potential, and the sum of the capacitors is CX + CY.
- First, we will explain using the example of a DA converter. In this case, the operating modes are divided into positive signal output and negative signal output, and within that, they are also divided into discharge mode and output mode. The discharge mode for positive signal output and the discharge mode for negative signal output are shown in Figure 2 and 411i1, respectively, and the output peak mode is shown in Figure 3. is the same as in the case of , but shows the output voltage; the configuration of the capacitor array 30 and the capacitor is different. The output voltage in the case of a positive signal is as shown by the following equation (1)K.
負信号O場合の出力電圧は次式(2)に示す如くな為。The output voltage when the negative signal is O is as shown in the following equation (2).
式(1)と(2)から正信号の場合と負信号の場合とで
第1図に示すコンダンずプレイ3のスイッチSw1〜8
Wnを動作さす制御信号が異なることが判る〇ヒのこと
から従来ODA変換器は第5図に示すようにディジタル
入力信号からコンデンサプレイ3に与へる制御信号を作
るデコーダ回路IKお−て正信号用デコード回路S及び
負信号用デプード回□
路6及びそれのセレクト回路4を必要としデコーダ回路
1が複雑になJj@路規模が大きくなる欠点がある。From equations (1) and (2), the switches Sw1 to 8 of the conductor play 3 shown in FIG. 1 in the case of a positive signal and the case of a negative signal.
Since it can be seen that the control signals that operate Wn are different, the conventional ODA converter has a decoder circuit IK that generates a control signal applied to the capacitor play 3 from a digital input signal as shown in Fig. 5. It requires a signal decode circuit S, a negative signal decode circuit 6, and its select circuit 4, which has the disadvantage that the decoder circuit 1 is complicated and the circuit scale becomes large.
次にAD変換器の例で説明する。この場合はまづII7
図に示す如くコンデンサアレイの全コンデンサCムを放
電する。次に第8図に示す如く、アナ四グ入力をVl)
iよ)入力し比較器7の出力にて正の信号か負の11号
かの判定をする。次に正信号の場合は第9図に示すサン
プリングモードで負信号の場合は第11図に示すサンプ
リングモードでアナ四グ電圧をサンプリングしてコンデ
ンサプレイの全=ンデンサCムを充電する。次に第10
図に示す逐次比較モードで比較器70入力竜圧がOにな
るようにしてディジタル出力を得るわけである。正の4
1号の場合はサンプリングモードでコンデンサCムを充
−する電荷C1次式(3)の″如くなる。Next, an example of an AD converter will be explained. In this case, Maz II7
All capacitors C in the capacitor array are discharged as shown in the figure. Next, as shown in Figure 8, change the analog input to Vl)
i) is input, and the output of the comparator 7 determines whether it is a positive signal or negative No. 11. Next, in the case of a positive signal, the analog voltage is sampled in the sampling mode shown in FIG. 9, and in the case of a negative signal, in the sampling mode shown in FIG. 11, to charge the total capacitor play. Then the 10th
In the successive approximation mode shown in the figure, the input pressure of the comparator 70 becomes O to obtain a digital output. Positive 4
In the case of No. 1, the charge C charged in the capacitor C in the sampling mode is expressed by the linear equation (3).
Q=OA (VIN−V)=”・(3)次に逐次比較
そ一ドでコンデンサCXとCY 。Q=OA (VIN-V)=”・(3) Next, in the successive approximation mode, capacitors CX and CY are connected.
比を変化さして比較67の入力電圧をOとするのでアナ
關グ入力電圧は次式(荀で示される。Since the input voltage of the comparator 67 is set to O by changing the ratio, the analog input voltage is expressed by the following equation (x).
負信号の場合はサンプルモードでコンデytcムを充電
する電荷Qは次式(荀の如くなるQ m CA V I
w =”” (酔次に逐次比1m!Jl−ドで=ンデ
ンサCxとCY。In the case of a negative signal, the charge Q that charges the conductor ytcm in sample mode is calculated by the following formula (Q m CA V I
w = ”” (Successive ratio 1m for the first time! Jl-de = Ndensa Cx and CY.
比を変化さして比asyo入力電圧なOと1するのでア
ナレグ入力電圧は次式(@で示される。Since the ratio is changed and the ratio asyo input voltage O is 1, the analog input voltage is expressed by the following formula (@).
上記(4X6)式に示す値をディジタル出力として取出
すわけである。The value shown in the above equation (4×6) is taken out as a digital output.
式(4XIから正信号の場合と負信号の場合とで第6図
に示すコンデンサアレイ10のスイッチSW1〜8Wn
を動作さす制御信号が異なることが判る。From the formula (4
It can be seen that the control signals that operate the are different.
このことから従来のADK換器は第12図に示す如くア
ナ襲グ入力信号からコンデンサアレイ10に与へる制御
信号を作るデコーダ回路8において正信号用デコード回
路12及び負信号用デコード回路13及びそれのセレク
)Id路11を必要としデコーダ回路8i複雑となシ回
路−機が大きくなる欠点はDA変換器の場合と同様で6
る◎本発@O8的社上記の欠点をなくするために革−参
照電位11:lンデンサアレイ型符号変換器において、
参照電位と接地電位の接続を被変換信号O正負によりて
切ヤ替えることkよって、デコーダ回路を簡単にし安価
に出来る符号変換器の提供にある。For this reason, in the conventional ADK converter, as shown in FIG. 12, a decoder circuit 8 that generates a control signal applied to a capacitor array 10 from an analog input signal includes a positive signal decoding circuit 12, a negative signal decoding circuit 13, The drawback is that it requires Id path 11 and the decoder circuit 8i is complicated and the device becomes large, as in the case of DA converter.
In order to eliminate the above-mentioned drawbacks, in a leather-reference potential 11:l capacitor array type code converter,
An object of the present invention is to provide a code converter whose decoder circuit can be simplified and made inexpensive by switching the connection between a reference potential and a ground potential depending on the positive and negative signals O to be converted.
本発明は上記の目的を達成する丸めに′:1ンデyサア
レイと該コンデンサプレイの各コンデンサを参照電位ま
たは接地電位に切替接続するスイッチと該″:syデン
!アレイに接続されたデコーダ回路を備えてなる単−参
照電位型=ンデンサアレイ渥符号変換器において、該コ
ンデンサアレイに接続する参照電位及び接地電位の接続
を入れかえるスイッチを具備し、該スイッチを被変換信
号の符号によりて制御する仁とを特徴とする符号変換器
の提供である。To achieve the above object, the present invention includes a rounding array of 1 decoders, a switch for selectively connecting each capacitor of the capacitor array to a reference potential or ground potential, and a decoder circuit connected to the array. A single-reference potential type = capacitor array code converter comprising: a switch for switching the connection of the reference potential and ground potential connected to the capacitor array; and the switch is controlled by the sign of the signal to be converted. The present invention provides a code converter characterized by:
以下本発明の実施例につき図に従りて説明する0第13
図は本発明のDA変換器のブロック構成図、1s14図
は本発明のAD変換器のブロック構成図である。Embodiments of the present invention will be explained below with reference to the drawings.
The figure is a block diagram of the DA converter of the present invention, and the figure 1s14 is a block diagram of the AD converter of the present invention.
図中第sL第12図と同じ機能のものは同一記号で示し
である@
Is、16はデコーダ回路、1?は逐次比較レジスタ、
8Wム、5w1t、swA’、8WB’社参照電位と接
地電位の切替スイッチ、コンデンサプレイ3.10の回
路紘第1図、第6図に示す◎まづDA変換器の場合につ
き説明する。#13111に示す出力そ一ドで例へば負
信号の場合、参照電位と接地電位の接続をデコーダ回路
15よりの制御信号によりスイッチ8WA、8WBを動
作さして反転する。このことによりコンダンtcz、c
yの位置が逆になるので(2)弐に対応して出力電圧線
次式(力に示す如くなる@
即ち(IM?)式よ)コンデンサアレイ3のスイッチS
W1〜8Wnを動作さす制御信号は同一でよいことが判
る。In the figure, parts with the same functions as those in Figure 12 are indicated by the same symbols.@Is, 16 is a decoder circuit, 1? is a successive approximation register,
8W, 5w1t, swA', 8WB' reference potential and ground potential changeover switch, capacitor play 3.10 circuit diagrams shown in Figures 1 and 6. First, the case of the DA converter will be explained. For example, if the output signal shown in #13111 is a negative signal, the connection between the reference potential and the ground potential is reversed by operating the switches 8WA and 8WB by the control signal from the decoder circuit 15. This allows condan tcz, c
Since the position of y is reversed, the output voltage linear equation (as shown in the force @, that is, the (IM?) equation) corresponds to (2) 2. Switch S of capacitor array 3
It can be seen that the control signals for operating W1 to Wn may be the same.
次にAD変換器の場合につ自説明する0例へば負信号の
場合第10図に示す逐次比較モードで参照電位と接地電
位の接続をデコーダ回路16よシの制御信号によ〕スイ
ッチ8WA’、8WB’を動作さして反転する◇このこ
とによシコンデンサCHI CTO位置が逆になるので
アナログ入力電圧は(句式に対応して次式(荀に示す如
くなる◎即ち伽)(吟式より:をンデンサアレイ10の
スイッチSWI〜BWhを動作さす制御信号は同一でよ
いことが判る。Next, in the case of an AD converter, as an example, in the case of a negative signal, in the successive approximation mode shown in FIG. 8WB' is operated and inverted. ◇As a result, the capacitor CHI CTO position is reversed, so the analog input voltage becomes It can be seen that the control signals for operating the switches SWI to BWh of the capacitor array 10 may be the same.
即ちDA変換□器、AD変換器の場合共、デコーダ回路
1!S、16のコンデンサアレイ3. l0C)スイ
ッチSW、〜8Wnの制御信号を、正負の信号の場合に
分けて考へる必要がなく七しク)It路も工費になシ簡
単になることが判る。In other words, in both the DA converter and AD converter, the decoder circuit 1! S, 16 capacitor array3. It can be seen that there is no need to consider the control signals of the switches SW and -8Wn separately for positive and negative signals, and that the It path also becomes simpler in terms of construction costs.
以上詳mKa明した如く本発明によれば単一参照電位の
コンデンサアレイ型符号変換器のデコーダ回路構成を簡
単に出来回路規模を縮少出来るので安価にできる効果が
ある0As explained in detail above, according to the present invention, the decoder circuit configuration of a capacitor array type code converter with a single reference potential can be easily configured and the circuit scale can be reduced, resulting in an effect of lowering the cost.
第1図II/E5図は従来のDA変換器の例のブーツク
構成図、第6図第1−図は従来のAD変換器O例のブー
ツク構成図、第13図は本発IJiODA変換器の例の
プ四ツク構成図、第14図は本発明OAD変換器の例の
プ田ツク構成図、jgZ図〜第4図紘図線変換器の動作
原理図、第7図〜第11図はAD変換器の動作原理図で
ある。
図中1. 8. 15. lfiはデコーダ回路、2
唸バツフアアンプ、3.10はコンデンサアレイ、4.
11はセレクタ回路、S、tZは正信号用デコード回路
、6.13は負信号用デコード回路、7は比較器、9,
14.17は逐次比較レジスタ、C1〜Cmはコンデン
サプレイの各コンデンサ、Codスンデンサアレイの各
=ンデyv−の総和、SW1〜8Wnはコンデンサプレ
イのスイッチ、8WA、8WB、8WA’、8WB’、
8WD。
8WGはスイッチ、Vは参照電位、VOUTはアナ四グ
出力、vINはアナ四グ入力、CXt cyは参照電位
又は接地電位に接続されるコンデンサの和綽 5 j
テ”イジタJL/λ〃信号
耳8目
’4 q vn
V
5#10口
薯110
11zti’1
wCFIG. 1 II/E5 is a boot-stack configuration diagram of an example of a conventional DA converter, FIG. 6, FIG. FIG. 14 is a block diagram of an example of a four-way converter, FIG. 14 is a block diagram of an example of an OAD converter of the present invention, and FIGS. FIG. 3 is a diagram of the operating principle of an AD converter. 1 in the figure. 8. 15. lfi is a decoder circuit, 2
3.10 is a capacitor array, 4.
11 is a selector circuit, S and tZ are positive signal decoding circuits, 6.13 is a negative signal decoding circuit, 7 is a comparator, 9,
14.17 is a successive approximation register, C1 to Cm are each capacitor of the capacitor play, the sum of each =nd yv- of the Cod sensor array, SW1 to 8Wn are the switches of the capacitor play, 8WA, 8WB, 8WA', 8WB' ,
8WD. 8WG is a switch, V is a reference potential, VOUT is an analog output, vIN is an analog input, CXtcy is a capacitor connected to a reference potential or ground potential. 8th '4 q vn V 5#10 mouthpiece 110 11zti'1 wC
Claims (1)
サを参照電位型た紘接地電位に切替接続するスイッチと
誼=ンデンサアレイに接続され九デ=−メ回路を備えて
なる単−参照電位型コンデンサアレイ型符号変換器にお
いて、鋏;ンデンサアレイに接続する参照電位及び接地
電位の接続を入れかえるスイッチを具備し、骸スイッチ
を被変換信号の符合によって制御することを特徴とする
符号変換器。A single-reference potential type capacitor array type code comprising a capacitor array, a switch for switchingly connecting each capacitor of the capacitor array to a reference potential type ground potential, and a nine-dimensional circuit connected to the capacitor array. 1. A code converter, characterized in that the converter is equipped with a switch for switching the connection of a reference potential connected to a capacitor array and a ground potential, and the skeleton switch is controlled according to the sign of a signal to be converted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11814281A JPS5820028A (en) | 1981-07-28 | 1981-07-28 | Code converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11814281A JPS5820028A (en) | 1981-07-28 | 1981-07-28 | Code converter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5820028A true JPS5820028A (en) | 1983-02-05 |
JPS6319096B2 JPS6319096B2 (en) | 1988-04-21 |
Family
ID=14729104
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11814281A Granted JPS5820028A (en) | 1981-07-28 | 1981-07-28 | Code converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5820028A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60136459A (en) * | 1983-12-26 | 1985-07-19 | Toshiba Corp | Dtmf signal generator |
JPS60136461A (en) * | 1983-12-26 | 1985-07-19 | Toshiba Corp | Dtmf signal generator |
JPS61157119A (en) * | 1984-12-28 | 1986-07-16 | Nec Corp | Analog-digital converting circuit |
US6243118B1 (en) | 1996-12-05 | 2001-06-05 | Nippon Steel Corporation | Electrostatic recording apparatus for supplying vaporized solvent and liquid toner to an electrostatic latent image |
JP4813568B2 (en) * | 2006-02-02 | 2011-11-09 | ナショナル ユニヴァーシティー オブ シンガポール | Analog-to-digital converter |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11201299B2 (en) * | 2017-05-04 | 2021-12-14 | Universal Display Corporation | Organic electroluminescent materials and devices |
-
1981
- 1981-07-28 JP JP11814281A patent/JPS5820028A/en active Granted
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60136459A (en) * | 1983-12-26 | 1985-07-19 | Toshiba Corp | Dtmf signal generator |
JPS60136461A (en) * | 1983-12-26 | 1985-07-19 | Toshiba Corp | Dtmf signal generator |
JPS61157119A (en) * | 1984-12-28 | 1986-07-16 | Nec Corp | Analog-digital converting circuit |
US6243118B1 (en) | 1996-12-05 | 2001-06-05 | Nippon Steel Corporation | Electrostatic recording apparatus for supplying vaporized solvent and liquid toner to an electrostatic latent image |
US6509918B1 (en) | 1996-12-05 | 2003-01-21 | Nippon Steel Corporation | Electrostatic recording apparatus and image density control method thereof |
JP4813568B2 (en) * | 2006-02-02 | 2011-11-09 | ナショナル ユニヴァーシティー オブ シンガポール | Analog-to-digital converter |
Also Published As
Publication number | Publication date |
---|---|
JPS6319096B2 (en) | 1988-04-21 |
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