JPS58182853A - 半導体素子のカプセル封じ法およびこの方法により得られる素子 - Google Patents

半導体素子のカプセル封じ法およびこの方法により得られる素子

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Publication number
JPS58182853A
JPS58182853A JP58056817A JP5681783A JPS58182853A JP S58182853 A JPS58182853 A JP S58182853A JP 58056817 A JP58056817 A JP 58056817A JP 5681783 A JP5681783 A JP 5681783A JP S58182853 A JPS58182853 A JP S58182853A
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JP
Japan
Prior art keywords
metal
connection
chip
substrate
alloy layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58056817A
Other languages
English (en)
Inventor
ジヨルジユ・ロシユ
ジヤツク・ランテ−ル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel CIT SA
Compagnie Industrielle de Telecommunication CIT Alcatel SA
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Filing date
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Application filed by Alcatel CIT SA, Compagnie Industrielle de Telecommunication CIT Alcatel SA filed Critical Alcatel CIT SA
Publication of JPS58182853A publication Critical patent/JPS58182853A/ja
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は半導体素子、とくに非常に１！ｌ雑な素子のカ
プセル封じ法及びこの方法によってカプセルに封入され
た素子に係る。
非常に複雑な半導体素子のカプセル封じは、とくに目指
す製造が充分な数量に達しない場合には使用技術がしは
しば高価につく隅如において集積回路の製造の１要な要
素である。例えばいわゆるＴＡＢと呼ばれる、支持膜上
へのチップの配置技術の場合がそうである。
提起される主要な問題は、製造される単位素子の寸法を
最大限に縮小することによって接続可能数をふやすこと
が求められる限）において、集積回路を外部と結合する
ことをａＪ能ならしめる接続法上実現することである。
ところで最も大きなスペースを要求する吃のは外部との
必要な接続である。何故ならば集積回路の内部に完成さ
れる結線に合わせて外部結線を縮小することはできない
からである。
実際に、もし金属製薄板から作られる金属接続格子上へ
溶接によってチップを配置するならば、溶接前の格子の
機械的保持応力は接続チップの寸法の縮小を制限する。
もし反対に、仮に基板がわらかしめ金属層で覆われてい
るとすれば、被ｙ１′ｆｒ介しての選択層、１九は加算
的写真平板′ｔたは場合によっては減算的写真平板のよ
うな、マイクロエレクトロニクスに於いては一般的であ
るさ壕ざ壕な技術によって基板上に非常に小寸法の接続
格子を作ることが可能でＬＬ接続格子をその支持絶縁基
板から分離することはで衰ず、また従ってこれらの結締
をチップと同じ側に買くということを別とすれば、この
ようにして形成された接続格子を利用することはできな
い。但しこれは本発明の目的ではない。
本発明は従って半導体素子、特に非常に小寸法の接続格
子を持ち、カプセルに封入された素子の製造を可能なら
しめる非常に複雑な素子のカプセル封じ法を目的とする
。
本発明の特徴によれば、各素子を外部と結合するだめの
結線は仮の金属製基板を榎う融点の低い合金製導電層上
に配置された金属格子の形でａｍされ、各素子の取付は
及び結合と硬化樹脂を用いた不動化の後、合金層の溶解
によシ仮基板を取除くことによって、素子の外部との電
気的及び／または熱的接続のための接続帯の面を出現さ
せる。
さらに、本発明の対象をなす方法によれば、外部との接
続を保証するための同一平面上の金属接続帯との接続線
を有する硬化樹脂内に不動化された少くとも１個のチッ
プを含むカプセル封じされた素子は、融点の低い合金層
によって金属接続帯と結合する仮のｇｌ、ｖｉ＆金属基
板としても機能し、この合金層の清解り仮の基板を取除
き、外部との電気的及び／または熱的接続のための接続
帯の面を出現させることを可能にする。
さて次に添付図面を参照して、本発明に基くカプセル封
じ法及びこの方法によって得られる素子について詳しく
説明する。
第１図に示す半導体素子は習慣的に、チップ１内に包含
される回路を素子の外部と電気的に確実に接続するため
の金属接続帯の格子３（例えば３Ａ　、３Ｂ　、３Ｃ，
３Ｄ　、ＢＥ）に接続導線２（例えば２Ａ　、２Ｂ　、
２Ｃ，２Ｄ　、２Ｅ）によって結合されたけい素テップ
１を含んでいる。図示のへ体例では、接続帯８とあらか
じめ同一平面上に配置された金槁１４は、動作によって
生じてくる熱量を排出するために、チップ１の外部との
熱的接続を保証する。
チップ、接続導線２及び接続帯３は電気的絶縁と、導線
２及びチップ１の相互間及び接続帯３及び４に対する不
動化とを保証する硬化樹脂５によって被覆８れる。
図示されていない外部回路に通じている図示されていな
い結線との接続を保証するためのこれらの接続帯３及び
４の面は、素子の使用前に破損と汚染から接続帯を確実
に保護する、いわゆる一時的な、金属基板７を覆う融点
の低い合金導電層６に溶接される。合金層６の溶解は素
子を外部と結合するのに役立つ接続帯３及び４の面を出
現させる仮の基板７の除去を可能にする。
本発明によれに、カプセル封じ法は次のように実施され
る。まず第一に、ふつう導電性の金属基板７上に融点の
低い導電性の合金製薄層６を形成する。
基板は例えば標準的な金属板よｐ成ｐ、合金は例えばこ
れを付着させる金属の清接及び錫めっきを可能ならしめ
る錫−亜鉛タイプである。この合金層は任意の適尚な手
段によって付着すれによく、例えに、金属接続帯を形成
する次の工程時に融解温度の比較的高い錫−亜鉛一銅タ
イブの三成分合金の形成を避けるために充分な厚さの電
解層でお９、例えば１０乃至３０ミクロンの最小厚さを
選ぶことができよう。
（以下余白） この第一の工程は、融点の低い合金であらかじめ僚われ
た金属プレートまたは帯材を用いることを目指す限りに
おいては次の工程に必ずしも直接つながらなくともよい
。
第二に、金属層６に配置された格子の形で金属接続帯３
及び４が形成される（第２図）。
このため数種類の技術が可能であって、そのうちの第一
の技術は、合金層への接続帯の溶接後に取除かれる、図
示されてｂない一時的な接続によって相互的に接続され
るさまざまな接続帯３及び４を含むあらかじめ切断され
た金属薄板を使用するというものである。この方法は得
られた素子を含む硬化樹脂によって次に耐えられること
になる機械的な応力に耐えるだめの金属層６上に接続帯
３及び４を溶接する際に一時的接続を利用することがで
きる限りにおいて、チップの接続帯が占有する面を大き
く縮減することを可能にする。
本発明の変形例によれば、金属接続格子を形成するため
の金属は基板７によって支持される合金層６上に配置さ
れる。格子は例えば被膜を介して。
銅またはニッケルのような金属の選択的な１ｉ着によっ
て、または特に写真平板技術に従う一様で全体的な金ｐ
Ａ鳩の選択的な除去によって得られる。
その結果得られるのは、本発明に従ってカプセル封じさ
れる素子の同時的及び／又は連続的製造を可能ならしめ
る。第４図及び第５図に示されたような規則的な反復模
様に従ってあらかじめ配置された金属格子である。
さまざまな接続帯３及び４が構成する接片の厚さ及び寸
法並びにそれらの間隔は普通の電気的応力の関数として
選定され、この場合このようにして得られた接片はそれ
らの製造の基礎をなす合金層。
にぶって仮基板７上に固く固定されるから、あらかじめ
切断された薄板から作られる格子の使用によって導かれ
る機械的応力が介入することはない。
それゆえ合金によｐ櫟われた仮基板７上に各チップｌに
ついて最小寸法の接続格子を形成するため、マイクロエ
レクトロニクスに於いては一般的である技術を用いるこ
とが可能である。
つぎにチップ１をそれぞれの接続帯４上に取伺け、さら
に第３図に示されるように接続環ｍ２Ａ。
２Ｂ・・・を介して接続帯４上のチップ１と接続帯３Ａ
、３Ｂ・・・というふうに、接続環＃１２によって対応
する接続帯３にチップ１の電気的接続を行う。
これに用いられる手段は接続帯を有する絶縁基板上にチ
ップを位置決めし、接続するために一般的に用いられて
いる方法である。
各々の素子の検校はチップ１を覆う鋳造ないし成形され
た硬化樹脂５を用いて行われ、接続導線２及び接続帯３
は旧来法により同様に製造される。
この樹脂の冷却または重合による硬化は各々の素子のさ
まざまな要素１，２．３及び４を相互固定させることを
可能ならしめる。
樹脂５の硬化後、比較的低い温度での単純な加熱による
合金層６の溶解は小寸法の金属接続格子の形成を可能に
していた仮の金属基板７の除去を可能にする。
素子の製造工程の終了時かまたは素子の完成後かに行う
ことができる仮基板７の除去は、外部との電気的及び／
または熱的結合のための接続帯３及び４の面を出現させ
ることを可能にする。
素子完成直前に於ける仮基板７の除去は、衝撃ま九は摩
擦による破損に対して、および外部との接続が得られる
接続帯部分の汚染に対して確実に防謹を行うと込う利点
を提供する。
合金層の溶解はさらに接続帯の無用面上に錫めっき被膜
を存続させ、これによって図示されていない外部からの
結線の１ｗ接にふつうは必要とされる錫めっき作業を省
くことができる。
第２図及び第３図に示されているように、複数の素子を
同時に製造することも勿論可能であり、また金属製接続
格子は、チップｌの寸法に相当する寸法を有する熱拡散
接片４がそれぞれ衛生状の接続帯３によってとり巻かれ
るという形にあらかじめ配列された規則的な反復模様を
示す。各々の素子は樹脂内への封入と樹脂の硬化の後、
仮基板の除去の前か後かに、のこ引きまたは切断によっ
て相互に分離される。
第４図ｅよ、接続帯３及び４が露出されたこのような単
位素子をあられす。
本発明の変形例によれば、第５図に示されているように
、行列イｋに配列された同一接片により構成される規則
的模様に従って接続金属格子が作られている。チップの
下側に配置された熱拡散帝は従って周囲の電気接片３と
同−形のＭＭをほどこした複数の接片３によって構成さ
れる。
このことはさ壕ざまな素子について同じ模様を用いるこ
とを可能ならしめ、これはさまざまなチップを有する少
量の素子を製造する必要がある場合には有利である。
【図面の簡単な説明】
第１図は本発明に基いて具体化された素子の一部分を取
除いた説明図。 第２図は本発明に基く素子のカプセル封じ法の中間工程
に相当する金属層１合金層、仮基板の全体図、 第３図は本発明に基くカプセル封じ法の後半工程に相当
する、第２図に基〈チップの取付は及び接続をあられす
全体図、 第４図は本発明に基いてカプセルに封入した素子の下面
図、及び 第５図は本発明の変形例に従うカプセル封入素子の下面
図である。 １・・・けい累チップ、２・・・接続導線、３・・・接
続用金属格子、４・・・金ＪＩ！帝、５・・・硬化樹脂
、　　６・・・合金層、代理人弁場士今　　村　　　元 ＦＩＧ、’ｔ

Claims (8)

    【特許請求の範囲】
  1. （１）個々の半導体素子を外部と結合するだめの接続帯
    を、仮の金属製基板を覆う融解点の低い合金製導電層上
    に配置された金属格子の形で実現すること、及び、素子
    の各チップの取付は及び接続、次に硬化樹脂を用いた不
    動化の後、樹脂の硬化工程の後で合金層を融解させ、こ
    れによって仮基板を除去し、さらにこのようにしてカプ
    セル封じされた素子と外部との電気的及び／または熱的
    接続のための接続帯の間を表われさせることを可能にす
    ることｔ−特徴とする半導体素子及び特に非常に複雑な
    素子のカプセル封じ法。
  2. （２）金属格子が金属薄板の切断によって得られること
    、及び金属格子が合金層上に加熱によって溶接されるこ
    とを４ｉｉＰ黴とする特許請求の範囲第１項に記載のカ
    プセル封じ法。
  3. （３）金属格子が合金層上に選択的収縮によって選択的
    または全体的に生成された金属層から得られる仁とを特
    徴とする特許請＊の範囲第１項に記載のカプセル封じ法
    。
  4. （４）以下の工糧段階、即ち、 板金属基板上への融点の低い合金層の付着、合金層上で
    の接続格子を形成する丸めの金属層の生成、 格子の接続帝王へのチップの固定及び配線、チップによ
    ｐ成る各素子、その接続導線及びその接続帯を硬化樹脂
    の鋳造または成形により核種すること、 樹脂の硬化、 合金層の融解による、素子を支える金属層及び仮基板の
    解離、及び素子の外部との電気的及び／または熱的接続
    のための接続相のこのようにして錫めっきされた面を出
    現させること、 を含むことを特徴とする特許請求の範囲第１項に記載の
    カプセル封じ法。
  5. （５）金属層の付着が、適用されたチップの寸法と等し
    い寸法を有する熱拡散用の中央帯とこの中央帯の周囲に
    配置された衛星状の接続相とを含む規則的な反復模様に
    従って行われ、模様のさまざまな帯域がチップの取付け
    、接続導線の接続及びカプセル樹脂の硬化の後、切断法
    によって機械的に分離され得る単位素子の境界を定める
    ことを特徴とする特許請求の範囲第１項にｈピ載の半導
    体素子のカプセル封じ法。
  6. （６）金属層の付着が、チップの適用された数個の接片
    によって各チップの下１１１Ｖｃ熱拡散帝を形成し、さ
    らにチップから出る接続導線をこのチップをと９囲む接
    片に接続することを可能にするようにして行列状に配列
    した複数個の同一接片を含む規則的な反復模様に従って
    、このようにして形成された単一素子がチップの取付け
    、接続導線の接続及び、カプセル樹脂の硬化の後、切断
    法によって機械的に分離可能であるようにして行われる
    ことｔ−％黴とする特許請求の範囲第１項に記載の半導
    体素子のカプセル封じ法。
  7. （７）　　外部から発する接続導線の溶接に先立って行
    われる接続相の錫めっきが、仮基板と金属層の間に配置
    された合金層の融解による基板の除去に際して確保され
    ることを特徴とする特許請求の範囲第１項に記載の半導
    体素子のカプセル封じ法。
  8. （８）融点の低い合金層ＶＣよって同一平面上の接続金
    属帯と結合した仮の保賎金属基板を含んでお）、この仮
    基板の融解はこの基板を取除き、素子の外部との電気的
    及び／又は熱的接続のだめの接続相の面を出現させるこ
    とを可能にすることを特徴としておｐ１外部との接続を
    保証すゐための同一平面上の金属接続帯との接続導線を
    有し、硬化樹脂内に不動化された少くとも１個のチップ
    を含むカプセル封入形の半導体素子。
JP58056817A 1982-04-01 1983-03-31 半導体素子のカプセル封じ法およびこの方法により得られる素子 Pending JPS58182853A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8205624 1982-04-01
FR8205624A FR2524707B1 (fr) 1982-04-01 1982-04-01 Procede d'encapsulation de composants semi-conducteurs, et composants encapsules obtenus

Publications (1)

Publication Number Publication Date
JPS58182853A true JPS58182853A (ja) 1983-10-25

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US (1) US4530152A (ja)
EP (1) EP0091072B1 (ja)
JP (1) JPS58182853A (ja)
DE (1) DE3369428D1 (ja)
FR (1) FR2524707B1 (ja)

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EP0091072A1 (fr) 1983-10-12
DE3369428D1 (en) 1987-02-26
FR2524707A1 (fr) 1983-10-07
EP0091072B1 (fr) 1987-01-21
US4530152A (en) 1985-07-23
FR2524707B1 (fr) 1985-05-31

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