JPS58122757A - 樹脂モ−ルド半導体装置 - Google Patents

樹脂モ−ルド半導体装置

Info

Publication number
JPS58122757A
JPS58122757A JP554382A JP554382A JPS58122757A JP S58122757 A JPS58122757 A JP S58122757A JP 554382 A JP554382 A JP 554382A JP 554382 A JP554382 A JP 554382A JP S58122757 A JPS58122757 A JP S58122757A
Authority
JP
Japan
Prior art keywords
resin
semiconductor chip
semiconductor device
chip
sealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP554382A
Other languages
English (en)
Inventor
Mitsuo Tashiro
光男 田代
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SEIKO KEIYO KOGYO KK
Original Assignee
SEIKO KEIYO KOGYO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SEIKO KEIYO KOGYO KK filed Critical SEIKO KEIYO KOGYO KK
Priority to JP554382A priority Critical patent/JPS58122757A/ja
Publication of JPS58122757A publication Critical patent/JPS58122757A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は樹Ｎ４−ルド牛導体装置の実装構造に係１４１
に氷島発振式電子腕時計の如き超小量半導体ｉｌ装置の
樹層対土の実装構造Ｋｌｌするものである。
近年、電子腕時計等における半導体チップの実装構造と
しては、超小型、薄型が強（要求さｎてお１、それに答
えるぺ龜有用な方法の一つとして、アリツブチッ装置の
フェイスダウンエツチングが増１しククある。こｎらの
技術の具体的な実施例として、現状の７工イメダウン実
装方式を用い究樹脂モールド半導体装置の実装構造を第
１１１１によって説明する。纂１図参）　、　ｅ）は従
来技術Ｋｓ？ける樹脂モールド半導体装置の実装構造を
示す、１は一路基板で、ガラスエポキシ又はセラ電ツタ
等からＩＥＪｌ、該回路基板ｌ上に社、エツチング等に
より”ｃｌ！ｔパ！−ン２が所定の形状に形成されてい
る。３は半導体チップで、＃半導体チップ３のパッドに
幌、低融点半田等で形成さｎた突起電極−・が形成され
ている。該突起電極３６は、導電パターン２へ位置決め
″ｇｆ′Ｌ、同時フェイスダウンｌンデンダ等の方法に
より結合されている。４は枠体で、プラスチッタ等の材
料から成形ｉ１３．回路基＠ｌＫ接層等の方法によって
固定されている、　ｓｕｅ棒体４は、早導体チツ１３ｔ
エポキシ樹脂□等から成るモールｅ部材５の樹脂封止時
のｆＩｌ、ｆＬｔ飢制する効果を有している。又纂１図
（ロ）は枠体を有する樹脂封止構造でＴｏｌｌ、第１１
１Ｃ＆）は枠体なしの樹脂封止構造である。
１１１（２）では、枠体４を使用している究め、枠体４
の価格、關路基［１への固定するための工程等によ為実
装費用の増加、又枠体４の固定スペースを必要とし、形
状の小厘薄鳳化を計る上で問題となる。ｘ図１＆では、
枠体４による実装費用の増加は解消ｓｎるが、形状の小
腫薄層化ｔｔｔｉ上で、大龜−開題ＦＪｋクエいた。
本発明の目的は、アエイスダウンｌンデンダ管用いた半
導体装置の実装構造における、半導体装置の樹脂封止Ｋ
かいて、半導体チップフェイス画と対向する回路基板面
Ｋｌライ溝等を設置するζ七により、前記の如龜従来技
１１ｆＫシける問題点を解決し、低儒格化、小型化薄層
化を可能にする半導体装置の樹脂封止の構造を提供す為
ことである、以下図面によ）本発明の具体例を詳記する
。
第１図は本発＠におけるフェイスダウン実装方式を用い
た樹脂モールド半導体装置の実装構造を示す、　１１は
回路基板で、ガラスエポキシ又はセラミーン１２−ＩＩ
＆所定の形状に形ｌＥされている。１３は半導体チップ
で、該半導体チップ１３の突起電極１３−は、前記導電
パターン稔へ位置決め−ｔｉれ、同時フェイスダウンｌ
ンデンダによって結合されてｖｈる。
１６は半導体チップを樹脂封止するためのｓ　ｌ１ｌｔ
ｌｌ’１−ルド部材１５ｇ、１５１１保持するＭ路基板
面のナツイ溝である。第２図（ロ）の１５・は液状封止
樹脂でＴｏＬ又第２図の）の１５＆はペレット状樹脂（
市販品では、日東電工巣１ペレット等がこ３に相轟する
］である０本発明による樹脂封止の加エエＳ＊は、第２
図の回路基板１１のナツィ溝１６へあらかじめ液状封止
樹脂１５６又はペレット状樹脂１５＆管供給しでおき、
次に回路基板１１上に手導体チップロ管アエイスダウン
ｌンデンダする。その後に、−路基＠　１１１反転させ
て、半導体チップロ儒より加ｌ＆１せ、半導体チップ１
３上面を第２ｍ−）の如（、樹脂封止する。
以上述べた通り、本発１ｊｌＫよれば一路基板上に半導
体チップを７エイスダウンポンデン／により塔載してな
る半導体装置における樹脂モールド封止を小型、薄型化
に且っ低価格で行なうことができる。又以上の方法は他
の床机な半導体装置の製造にも充分応用出来ることは明
らかである。
【図面の簡単な説明】
第１図（ロ）、Ｃ＆）はそれぞれ従来の樹脂モールド半
導体装置の断面図であ）、纂２図は本考案の一実施例の
新面図であり、ｈ）　、　（＆）はそｎぞｎ樹脂モール
ド部材が充填さｒＬ＊形態を示し、（６）は半導体チッ
プを樹脂封止した状態を示す。 １．１１．、ｌｌ？ｌ路基板　　２，１２．、導電パタ
ーン３．１３．、半導体チップ３ｇ、１３ｇ、、突起電
極４０．枠体　　５，１５８，１５＆ｚ樹ｊ１４−Ｊｌ
’部材、１６．、ｔライ溝。 以上 出願人　セイコー東葉工業株式会社 代理人　弁理士　最　上　　務

Claims (1)

    【特許請求の範囲】
  1. 導電パターンを有する回路基板上に半導体チップｔ７エ
    イスダウンｌンデンダにより塔載し、且り半導体チップ
    を樹脂毫−ルド郁材によりて、封止して威る雫導体装置
    において、１記關路基板の半導体チップフェイス面と対
    向すゐ位置に、前記樹脂毫−ルド部材を保持するための
    、サツイ溝を備えたことｔｅａとする、樹脂壁−ｋｒ手
    導体装置。
JP554382A 1982-01-18 1982-01-18 樹脂モ−ルド半導体装置 Pending JPS58122757A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP554382A JPS58122757A (ja) 1982-01-18 1982-01-18 樹脂モ−ルド半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP554382A JPS58122757A (ja) 1982-01-18 1982-01-18 樹脂モ−ルド半導体装置

Publications (1)

Publication Number Publication Date
JPS58122757A true JPS58122757A (ja) 1983-07-21

Family

ID=11614098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP554382A Pending JPS58122757A (ja) 1982-01-18 1982-01-18 樹脂モ−ルド半導体装置

Country Status (1)

Country Link
JP (1) JPS58122757A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304512A (en) * 1991-12-25 1994-04-19 Hitachi, Ltd. Process for manufacturing semiconductor integrated circuit device, and molding apparatus and molding material for the process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304512A (en) * 1991-12-25 1994-04-19 Hitachi, Ltd. Process for manufacturing semiconductor integrated circuit device, and molding apparatus and molding material for the process

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