JPS58106873A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58106873A JPS58106873A JP56204886A JP20488681A JPS58106873A JP S58106873 A JPS58106873 A JP S58106873A JP 56204886 A JP56204886 A JP 56204886A JP 20488681 A JP20488681 A JP 20488681A JP S58106873 A JPS58106873 A JP S58106873A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- nitride film
- silicon nitride
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 238000000927 vapour-phase epitaxy Methods 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 2
- 239000001257 hydrogen Substances 0.000 abstract description 2
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 2
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 2
- 238000005245 sintering Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 15
- 238000007796 conventional method Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
Abstract
Description
【発明の詳細な説明】 本発明は、ＭＮＯ８不揮発メ毫りの製造方法に関する。[Detailed description of the invention] The present invention relates to a method for producing MNO8 non-volatile film.
従来ＭＮＯ８素子の製造に関しては、シリコン酸化ｓＩ
を５０〜１００ム形成し、その上にシリコン窒化１１１
ｔ５００Ａ程度形成し、このシリコン酸化膜とシリコン
窒化膜の界面捕獲準位に電荷をトラップし、これにより
しきい＋１［電圧をシフトさせデンタ會記録する不揮発
メモリーとしている。ところが、実際のシリコン窒化膜
には、多くの準位が膜内に広く分布するため、シリコン
酸化膜をトンネル効果で通過した電荷（主に電子）は、
シリコン酸化膜−シリコン窒化膜界面だけでなくこのシ
リコン窒化膜内の準位に多くトラップされる。このこと
は、消去時、つまシゲート電極とシリコン基板層間に、
電圧を印加しても、ゲート電極近傍にトラップされてい
る電子は、基板へ逃げにくくなり、結果的に消去特性の
悪い不揮発メモリーとなり、問題となっている。Conventionally, for manufacturing MNO8 elements, silicon oxide sI
50 to 100 μm of silicon nitride 111 is formed on it.
A voltage of about 500 A is formed, charges are trapped in the interface trap level between the silicon oxide film and the silicon nitride film, and the threshold voltage is shifted by +1 to form a nonvolatile memory for recording data. However, in an actual silicon nitride film, many levels are widely distributed within the film, so the charges (mainly electrons) that pass through the silicon oxide film due to the tunnel effect are
Many of them are trapped not only at the silicon oxide film-silicon nitride film interface but also at levels within the silicon nitride film. This means that during erasing, there is a gap between the gate electrode and the silicon substrate layer.
Even when a voltage is applied, electrons trapped near the gate electrode are difficult to escape to the substrate, resulting in a nonvolatile memory with poor erasing characteristics, which is a problem.
従来これらの欠点を除く方法として、シリコン酸化膜−
シリコン窒化膜界面に、金属層とか、金属酸化物層を非
常に薄くコーティングすることが試みられているが、可
動イオン等の混入がさけられず、ゲート電極へのリーク
が生じ易くなり、信頼性に欠けるものであった。Conventionally, as a method to eliminate these drawbacks, silicon oxide film -
Attempts have been made to coat the silicon nitride film interface with a very thin metal layer or metal oxide layer, but this does not prevent the incorporation of mobile ions, which tends to cause leakage to the gate electrode, and reduces reliability. It was lacking in
そζで、本発明はトンネル効果により、侵入してきた電
荷上、効率よくシリコ／酸化膜−シリコン窒化膜界面に
、捕獲し、しかも、従来の方法にみられる。ゲー）１４
へのリークなどのないＭＮＯ＆不＃発メモリの製造方法
ｔ−提供するものである。Therefore, the present invention uses the tunnel effect to efficiently trap the incoming charge at the silicon/oxide film-silicon nitride film interface, which is different from conventional methods. Game) 14
The present invention provides a method for manufacturing MNO and non-current memory without leakage.
次に、本＠明の製造方法′ｆｒＰチャネルアルミゲ−）
ＭＮＯ８素子を実施例として詳述する。第１因か、工１
！ＩＩＴ［１１１図である。ｔずＭ型基板に、ソース、
ドレイン１０２會形成し、ゲート部に、２０［１〜５０
０ムの厚さのシリコン酸化＃１ｏｓｔ形成する。Next, the book @ Ming's manufacturing method 'frP channel aluminum gate)
An MNO8 element will be described in detail as an example. First cause, engineering 1
! IIT[Figure 111] On the tzuM type board, the source,
102 drains are formed, and 20 [1 to 50
Form a silicon oxide #1ost with a thickness of 0 µm.
（第１−一）】
アルミニア、窒素雰囲気で、前記のシリコン酸化膜１０
３を、５０〜１００ム残すようにして、熱望化を行い、
シップｙ＠化＃１０４１に形成する。(1-1)] The silicon oxide film 10 described above is grown in an aluminium and nitrogen atmosphere.
3, leave 50 to 100 meters and make it aspirational,
Form the ship as #1041.
シリコン窒化膜の展厚か不足の場合は、プラズマＣＶＤ
法などの方法をもって、もう一層シリコン窒化［１０５
會形成し、水素シンタによる熱処ｓｔ−行い欠陥を少な
くする。（第１図（ｂ））ｉＩｋ後に、ゲート電極１０
６として、アルミニウムを形成し、ＭＮＯ８素子は完成
する。If the silicon nitride film is insufficiently thick, plasma CVD
Another layer of silicon nitridation [105
A heat treatment using hydrogen sintering is performed to reduce defects. (FIG. 1(b)) After iIk, the gate electrode 10
As step 6, aluminum is formed, and the MNO8 element is completed.
次に、本発明によって製造した素子の特長上挙げる。Next, the features of the device manufactured according to the present invention will be listed.
（１１従来の方法では、ゲート酸化ａｔ−１ｓｏ〜１０
０λと非常に薄くしかもピンホール等欠陥のない膜を形
成する必要が６つ九が１本発明では、２０Ｇ−５００ム
とかなり厚いゲート酸化ａｔ形成すれはよく制御性が非
常に高くなる。(11 In the conventional method, gate oxidation at-1so~10
In the present invention, it is necessary to form a very thin film of 0λ and free from defects such as pinholes.In the present invention, the gate oxidation layer can be formed as thick as 20G-500μ and the controllability is very high.
（２） 熱窒化によって作られたシリコン窒化膜は、
欠陥か少なく信頼性が高い。(2) Silicon nitride film made by thermal nitriding is
High reliability with few defects.
ｔｓ＞ シリコン酸化膜−シリコン窒化膜界面が、非
常に安定しすぐれている。ts> The silicon oxide film-silicon nitride film interface is very stable and excellent.
以上のような特長点から、従来の製造方法にみられた消
去特性の悪さ、ゲート電極へのリークなどによる信頼性
の低さか、全て一掃できる。Due to the above-mentioned features, it is possible to completely eliminate the poor erase characteristics and low reliability caused by leakage to the gate electrode, which were observed in conventional manufacturing methods.
４、園内のｌ！明
ｓ１図（ＳＬＩ Ｏ）） （０１は本発明の実施例であ
る。4. L in the park! Figure s1 (SLIO)) (01 is an example of the present invention.
以上 出願人 株式会社瞠紡精工會that's all Applicant: Kazubo Seikokai Co., Ltd.
Claims (1)
ｅｍｉｃｏｎｄｕａｔｏｒ）素子の製造に於いてシリコ
ン酸化１ｓｔ−形成し、該シリコン酸化膜の一部を熱窒
化してシリコン窒化膜とし、その上に、気相成長法ある
いけ、プラズマ堆積法などにより異なるシリコン窒化膜
を形成することｔ−％黴とする半導体装置の製造方法。(11M) 10B (MetaA-Nitride-8
In the manufacturing of the semiconductor device, a silicon oxide film is first formed, a part of the silicon oxide film is thermally nitrided to form a silicon nitride film, and a different silicon layer is deposited on top of the silicon nitride film by vapor phase epitaxy, plasma deposition, etc. A method of manufacturing a semiconductor device in which t-% mold is formed by forming a nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56204886A JPS58106873A (en) | 1981-12-18 | 1981-12-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56204886A JPS58106873A (en) | 1981-12-18 | 1981-12-18 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58106873A true JPS58106873A (en) | 1983-06-25 |
| JPS6257263B2 JPS6257263B2 (en) | 1987-11-30 |
Family
ID=16498019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56204886A Granted JPS58106873A (en) | 1981-12-18 | 1981-12-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58106873A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7101749B2 (en) | 1998-12-09 | 2006-09-05 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50147877A (en) * | 1974-05-08 | 1975-11-27 | ||
| JPS511395A (en) * | 1973-11-07 | 1976-01-08 | Ici Ltd |
-
1981
- 1981-12-18 JP JP56204886A patent/JPS58106873A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS511395A (en) * | 1973-11-07 | 1976-01-08 | Ici Ltd | |
| JPS50147877A (en) * | 1974-05-08 | 1975-11-27 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7101749B2 (en) | 1998-12-09 | 2006-09-05 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
| US7479430B2 (en) | 1998-12-09 | 2009-01-20 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6257263B2 (en) | 1987-11-30 |
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