JPS5797630A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5797630A
JPS5797630A JP17325680A JP17325680A JPS5797630A JP S5797630 A JPS5797630 A JP S5797630A JP 17325680 A JP17325680 A JP 17325680A JP 17325680 A JP17325680 A JP 17325680A JP S5797630 A JPS5797630 A JP S5797630A
Authority
JP
Japan
Prior art keywords
layer
wafer
impurity
semiconductor device
irradiated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17325680A
Other languages
Japanese (ja)
Other versions
JPS6119102B2 (en
Inventor
Osamu Okura
Yukio Takano
Masao Tamura
Nobuyoshi Kashu
Naoji Yoshihiro
Masanobu Miyao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP17325680A priority Critical patent/JPS5797630A/en
Publication of JPS5797630A publication Critical patent/JPS5797630A/en
Publication of JPS6119102B2 publication Critical patent/JPS6119102B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To obtain favorable ohmic contact of a semiconductor device by a method wherein after a coat layer of an impurity to be diffused is formed on the back of a semiconductor wafer, a laser beam is irradiated to the desired part thereof. CONSTITUTION:Various elements 3 are formed on the surface of the silicon wafer 1. A solution containing the desired impurity (phosphorus, for example) is coated on the back 2 of the wafer 1 to form the coat layer 4. When the laser beam 5 is irradiated to the layer 4, the layer 4 and the surface region of the back 2 are fused, and the impurity comes in the wafer 1 to form a low resistance layer 6.
JP17325680A 1980-12-10 1980-12-10 Manufacture of semiconductor device Granted JPS5797630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17325680A JPS5797630A (en) 1980-12-10 1980-12-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17325680A JPS5797630A (en) 1980-12-10 1980-12-10 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5797630A true JPS5797630A (en) 1982-06-17
JPS6119102B2 JPS6119102B2 (en) 1986-05-15

Family

ID=15957065

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17325680A Granted JPS5797630A (en) 1980-12-10 1980-12-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5797630A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63211635A (en) * 1987-02-26 1988-09-02 Nec Corp Semiconductor device
US6498366B1 (en) 1990-02-14 2002-12-24 Denso Corporation Semiconductor device that exhibits decreased contact resistance between substrate and drain electrode
JP2005277116A (en) * 2004-03-25 2005-10-06 Elpida Memory Inc Semiconductor device and its manufacturing method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63211635A (en) * 1987-02-26 1988-09-02 Nec Corp Semiconductor device
US6498366B1 (en) 1990-02-14 2002-12-24 Denso Corporation Semiconductor device that exhibits decreased contact resistance between substrate and drain electrode
US6649478B2 (en) 1990-02-14 2003-11-18 Denso Corporation Semiconductor device and method of manufacturing same
US20040237327A1 (en) * 1990-02-14 2004-12-02 Yoshifumi Okabe Semiconductor device and method of manufacturing same
US6903417B2 (en) 1990-02-14 2005-06-07 Denso Corporation Power semiconductor device
US7064033B2 (en) 1990-02-14 2006-06-20 Denso Corporation Semiconductor device and method of manufacturing same
JP2005277116A (en) * 2004-03-25 2005-10-06 Elpida Memory Inc Semiconductor device and its manufacturing method
US7666761B2 (en) 2004-03-25 2010-02-23 Elpida Memory, Inc. Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JPS6119102B2 (en) 1986-05-15

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