JPS5790771A - Disk cash control system - Google Patents
Disk cash control systemInfo
- Publication number
- JPS5790771A JPS5790771A JP55167746A JP16774680A JPS5790771A JP S5790771 A JPS5790771 A JP S5790771A JP 55167746 A JP55167746 A JP 55167746A JP 16774680 A JP16774680 A JP 16774680A JP S5790771 A JPS5790771 A JP S5790771A
- Authority
- JP
- Japan
- Prior art keywords
- disk device
- cpu
- data
- write
- disk
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To reduce the writing time on a disk device viewed from a CPU and at the same time to avoid the occurrence of an error in the fault procession, by sending the end of the writing back to the CPU at the starting time point of the data writing of the disk device. CONSTITUTION:A disk cash contains I/O circuits 1 and 3 for a CPU and a disk device respectively, a cash memory 2, a control circuit 4 and an MPU5. A data write detecting circuit of the disk device is installed to the circuit 4. When the data is written to the disk device from the CPU, the write data is transferred to the disk cash. Then the start of writing of the disk device is detected by the detecting circuit in a lapse of a certain time after a prescribed quantity of the write data is sent to the disk device. Thus a write start detection signal is applied to an MPU5, and the end is checked for the reception of the write data from the CPU. Then a write end signal is sent back to the CPU if the reception of the data is through.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55167746A JPS5790771A (en) | 1980-11-28 | 1980-11-28 | Disk cash control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55167746A JPS5790771A (en) | 1980-11-28 | 1980-11-28 | Disk cash control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5790771A true JPS5790771A (en) | 1982-06-05 |
Family
ID=15855336
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55167746A Pending JPS5790771A (en) | 1980-11-28 | 1980-11-28 | Disk cash control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5790771A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59111558A (en) * | 1982-12-17 | 1984-06-27 | Nec Corp | Disk cache device |
-
1980
- 1980-11-28 JP JP55167746A patent/JPS5790771A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59111558A (en) * | 1982-12-17 | 1984-06-27 | Nec Corp | Disk cache device |
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