JPS6423354A - Duplex buffer memory control system - Google Patents
Duplex buffer memory control systemInfo
- Publication number
- JPS6423354A JPS6423354A JP62180551A JP18055187A JPS6423354A JP S6423354 A JPS6423354 A JP S6423354A JP 62180551 A JP62180551 A JP 62180551A JP 18055187 A JP18055187 A JP 18055187A JP S6423354 A JPS6423354 A JP S6423354A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- data
- error
- buffer memory
- control system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Advance Control (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To realize a buffer memory access with high reliability by using 1st and 2nd buffer memory circuits and carrying out the control to inhibit the writing actions to the 2nd buffer circuit. CONSTITUTION:The buffer memory circuits 1 and 2 are duplicated and therefore can read two data at one time. Furthermore both circuits 1 and 2 always hold the data of the same contents. In a first cycle of a writing state, the output data on an arithmetic circuit are written to the circuit 1 and a data register 13 respectively and at the same time checked by an error detecting circuit 14. This error checking result is set at an error flag 15. Then the contents of the register 13 are written to the circuit 2 in the next cycle based on the state of the error flag as long as the data includes no error. While a write inhibiting signal WI is turned on when the data has an error so that the writing actions are inhibited to the circuit 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62180551A JPS6423354A (en) | 1987-07-20 | 1987-07-20 | Duplex buffer memory control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62180551A JPS6423354A (en) | 1987-07-20 | 1987-07-20 | Duplex buffer memory control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6423354A true JPS6423354A (en) | 1989-01-26 |
Family
ID=16085254
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62180551A Pending JPS6423354A (en) | 1987-07-20 | 1987-07-20 | Duplex buffer memory control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6423354A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5197145A (en) * | 1988-09-20 | 1993-03-23 | Fujitsu Limited | Buffer storage system using parallel buffer storage units and move-out buffer registers |
US6038647A (en) * | 1995-12-06 | 2000-03-14 | Fujitsu Limited | Cache memory device and method for providing concurrent independent multiple accesses to different subsets within the device |
JP2011164975A (en) * | 2010-02-10 | 2011-08-25 | Fujitsu Ltd | Information processor |
-
1987
- 1987-07-20 JP JP62180551A patent/JPS6423354A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5197145A (en) * | 1988-09-20 | 1993-03-23 | Fujitsu Limited | Buffer storage system using parallel buffer storage units and move-out buffer registers |
US6038647A (en) * | 1995-12-06 | 2000-03-14 | Fujitsu Limited | Cache memory device and method for providing concurrent independent multiple accesses to different subsets within the device |
JP2011164975A (en) * | 2010-02-10 | 2011-08-25 | Fujitsu Ltd | Information processor |
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