JPS5760865A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS5760865A JPS5760865A JP55136272A JP13627280A JPS5760865A JP S5760865 A JPS5760865 A JP S5760865A JP 55136272 A JP55136272 A JP 55136272A JP 13627280 A JP13627280 A JP 13627280A JP S5760865 A JPS5760865 A JP S5760865A
- Authority
- JP
- Japan
- Prior art keywords
- output
- fet92
- test mode
- circuit
- goes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To reduce the number of protective resistors used by a method wherein the output buffer in an IC device is set at a predetermined state when the circuit detecting test mode is operating for detection and all output terminals can be connected together. CONSTITUTION:The output line in a test mode detection circuit 40 is ''0'' when an IC device 20 is in normal operation. At that time, in each of output buffers 61...63, an FET92 is OFF, and a push-pull buffer consisting of FETs90, 91 and an inverter 80 is driven by forming the output in an output terminal 40 as the reverse output of an input signal 70. With the circuit 40 detected to be in a test mode status, the output line 41 goes to ''1'' to turn on the FET92 and the input signal 70 is forcibly grounded 11 through the ON-resistor in the FET92. Therefore, the output terminal 4 goes to ''1'' to make all output terminals ''1''. Therefore, common connection is available and protective resistors in input and output pins can be saved at the time of tests by applying bias.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55136272A JPS5760865A (en) | 1980-09-30 | 1980-09-30 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55136272A JPS5760865A (en) | 1980-09-30 | 1980-09-30 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5760865A true JPS5760865A (en) | 1982-04-13 |
Family
ID=15171309
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55136272A Pending JPS5760865A (en) | 1980-09-30 | 1980-09-30 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5760865A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58222500A (en) * | 1982-04-20 | 1983-12-24 | マステク・コ−パレイシヤン | Starting of select mechanism |
| JPS604232A (en) * | 1983-06-22 | 1985-01-10 | Toshiba Corp | Method for designating test mode of lsi |
| JPS6081836A (en) * | 1983-10-07 | 1985-05-09 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Integrated circuit logic chip |
-
1980
- 1980-09-30 JP JP55136272A patent/JPS5760865A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58222500A (en) * | 1982-04-20 | 1983-12-24 | マステク・コ−パレイシヤン | Starting of select mechanism |
| JPS6237480B2 (en) * | 1982-04-20 | 1987-08-12 | Mostek Corp | |
| JPS604232A (en) * | 1983-06-22 | 1985-01-10 | Toshiba Corp | Method for designating test mode of lsi |
| JPS6081836A (en) * | 1983-10-07 | 1985-05-09 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Integrated circuit logic chip |
| JPH0533540B2 (en) * | 1983-10-07 | 1993-05-19 | Intaanashonaru Bijinesu Mashiinzu Corp |
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