JPS57201940A - Assignment system for memory digit - Google Patents
Assignment system for memory digitInfo
- Publication number
- JPS57201940A JPS57201940A JP8600981A JP8600981A JPS57201940A JP S57201940 A JPS57201940 A JP S57201940A JP 8600981 A JP8600981 A JP 8600981A JP 8600981 A JP8600981 A JP 8600981A JP S57201940 A JPS57201940 A JP S57201940A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- data
- digit
- memory device
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE:To improve the efficiency of program genration and that of the processing of a processor by enabling a processor to directly process arithmetic which requires digit assignment for data in a memory device by machine word instructions of the processor. CONSTITUTION:When data 23 having <=22 word length necessary for program processing is read out of a memory 21 by direct digit assignment, a processor 24 operates a direct digit assigning circuit 25 which discriminates direct digit assigning processing from an instruction operation part for machine word instructions. The circuit 25 is so connected that data from the memory device 21 is inputted directly, and assigned data with one-word length is read out of the memory device 21 and set in the buffer register 26 in the circuit 25. The processor 24 transfers only the assigned necessary data from the buffer register 26 to a register r2. Similarly, writing to the memory device 21 by direct digit assignment and arithmetic such as comparison and addition are carried out through the operation of the direct digit assigning circuit 25.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8600981A JPS57201940A (en) | 1981-06-04 | 1981-06-04 | Assignment system for memory digit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8600981A JPS57201940A (en) | 1981-06-04 | 1981-06-04 | Assignment system for memory digit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57201940A true JPS57201940A (en) | 1982-12-10 |
Family
ID=13874686
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8600981A Pending JPS57201940A (en) | 1981-06-04 | 1981-06-04 | Assignment system for memory digit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57201940A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5383537A (en) * | 1976-12-28 | 1978-07-24 | Ibm | Data processing system |
-
1981
- 1981-06-04 JP JP8600981A patent/JPS57201940A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5383537A (en) * | 1976-12-28 | 1978-07-24 | Ibm | Data processing system |
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