JPS57200985A - Buffer memory device - Google Patents
Buffer memory deviceInfo
- Publication number
- JPS57200985A JPS57200985A JP56084053A JP8405381A JPS57200985A JP S57200985 A JPS57200985 A JP S57200985A JP 56084053 A JP56084053 A JP 56084053A JP 8405381 A JP8405381 A JP 8405381A JP S57200985 A JPS57200985 A JP S57200985A
- Authority
- JP
- Japan
- Prior art keywords
- data
- buffer memory
- address
- outputted
- written
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To execute processing at a high speed, by merging a partial write data and its original data in a buffer memory, when a data of a main memory of an address, whose partial write has been requested exists in the buffer memory, and executing its full write in the main memory. CONSTITUTION:When write of a data of a 4-byte unit has been requested from an operation processor 1, its data is set to an input register of a buffer memory 3 and a store register 4 of a main memory 5. Also, a byte to be written is outputted to lines 20a-20d from a buffer mark register 6. On the other hand, an address to be written is outputted to a line 23, and whether a data of this address exists in the buffer memory 3 or not is decided by an address array 9. As a result, in case when it exists, a new data is merged in the buffer memory 3, also ''1'' is outputted from a forcing circuit 28, lines 21a-21d are all set to ''1'', and the data in the buffer memory 3 is full-written in the main memory 5 through a line 32.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56084053A JPS57200985A (en) | 1981-06-01 | 1981-06-01 | Buffer memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56084053A JPS57200985A (en) | 1981-06-01 | 1981-06-01 | Buffer memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57200985A true JPS57200985A (en) | 1982-12-09 |
Family
ID=13819751
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56084053A Pending JPS57200985A (en) | 1981-06-01 | 1981-06-01 | Buffer memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57200985A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61256455A (en) * | 1985-05-06 | 1986-11-14 | ウオング・ラボラトリ−ズ・インコ−ポレ−テツド | Information processing system |
JPS62212745A (en) * | 1986-03-14 | 1987-09-18 | Hitachi Ltd | Data processor having buffer memory |
JPH01316850A (en) * | 1988-06-17 | 1989-12-21 | Toshiba Corp | Cache memory system |
-
1981
- 1981-06-01 JP JP56084053A patent/JPS57200985A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61256455A (en) * | 1985-05-06 | 1986-11-14 | ウオング・ラボラトリ−ズ・インコ−ポレ−テツド | Information processing system |
EP0201848A2 (en) * | 1985-05-06 | 1986-11-20 | Wang Laboratories Inc. | Information processing system with enhanced instruction execution and support control |
JPS62212745A (en) * | 1986-03-14 | 1987-09-18 | Hitachi Ltd | Data processor having buffer memory |
JPH01316850A (en) * | 1988-06-17 | 1989-12-21 | Toshiba Corp | Cache memory system |
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