JPS57199052A - Data processing device - Google Patents
Data processing deviceInfo
- Publication number
- JPS57199052A JPS57199052A JP56084052A JP8405281A JPS57199052A JP S57199052 A JPS57199052 A JP S57199052A JP 56084052 A JP56084052 A JP 56084052A JP 8405281 A JP8405281 A JP 8405281A JP S57199052 A JPS57199052 A JP S57199052A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- interruption
- content
- signal
- execution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE:To generate an interruption when an arbitrary instruction is executed, by deciding whether an interruption is generated after the execution of instruction or not through the interpretation of the content of an instruction register with an instruction decode table and transmitting an interruption signal to a processor. CONSTITUTION:An address of an instruction executed next from a processor 1 is outputted to a bus 2 and the content of said address of a main memory 5 is outputted to a data bus 3. The processor 1 outputs an instruction fetch signal 4 and reads the content of the bus 3 and the instruction is interpreted and executed. The content of the bus 3 is stored in an instruction register 6 in synchronizing with the signal 4. An instruction decode table 7 decides whether the interruption is generated after the execution of the instruction or not. If decided as the generation of interruption, an interruption signal is outputted from the table 7 to a signal line 8, and after the execution of instruction, the interruption is generated. The table 7 is rewritable and whether the interruption is generated after the execution of instruction or not can be designated arbitrarily by rewriting the content.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56084052A JPS57199052A (en) | 1981-06-01 | 1981-06-01 | Data processing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56084052A JPS57199052A (en) | 1981-06-01 | 1981-06-01 | Data processing device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57199052A true JPS57199052A (en) | 1982-12-06 |
Family
ID=13819724
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56084052A Pending JPS57199052A (en) | 1981-06-01 | 1981-06-01 | Data processing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57199052A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60128534A (en) * | 1983-12-16 | 1985-07-09 | Nec Corp | Information processing unit |
EP0280890A2 (en) * | 1987-02-04 | 1988-09-07 | Sharp Kabushiki Kaisha | System and method for detecting the execution of an instruction in a central processing unit |
JPH04362745A (en) * | 1991-06-10 | 1992-12-15 | Agency Of Ind Science & Technol | Instruction tracing device |
-
1981
- 1981-06-01 JP JP56084052A patent/JPS57199052A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60128534A (en) * | 1983-12-16 | 1985-07-09 | Nec Corp | Information processing unit |
JPH0344329B2 (en) * | 1983-12-16 | 1991-07-05 | Nippon Electric Co | |
EP0280890A2 (en) * | 1987-02-04 | 1988-09-07 | Sharp Kabushiki Kaisha | System and method for detecting the execution of an instruction in a central processing unit |
JPH04362745A (en) * | 1991-06-10 | 1992-12-15 | Agency Of Ind Science & Technol | Instruction tracing device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5387640A (en) | Data processing unit | |
JPS57185545A (en) | Information processor | |
JPS54107645A (en) | Information processor | |
JPS5580158A (en) | False fault generation control system | |
JPS54122043A (en) | Electronic computer | |
JPS54117640A (en) | Memory address designation system | |
JPS57199052A (en) | Data processing device | |
JPS5694451A (en) | Microprocessor incorporating memory | |
JPS5326632A (en) | Common memory control unit | |
JPS5259537A (en) | Data processor | |
JPS5599656A (en) | Interruption processor | |
JPS55119750A (en) | Processor providing test address function | |
JPS6429933A (en) | Store buffer controller for buffer storage system | |
JPS5617450A (en) | Data collection system | |
JPS57191758A (en) | System for storing test program in main storage | |
JPS57164351A (en) | Debugging device | |
JPS5561858A (en) | Central operation control unit | |
JPS5593580A (en) | Buffer memory control system | |
JPS54156434A (en) | Jump system between pages | |
JPS5588139A (en) | Program write system | |
JPS56162151A (en) | Information processing device | |
JPS55162156A (en) | Data processor | |
JPS5621258A (en) | Failure storage system in central processing unit | |
JPS569853A (en) | Buffer invalidation system | |
JPS53140948A (en) | Interrupt processing system |