JPS5588139A - Program write system - Google Patents

Program write system

Info

Publication number
JPS5588139A
JPS5588139A JP16002778A JP16002778A JPS5588139A JP S5588139 A JPS5588139 A JP S5588139A JP 16002778 A JP16002778 A JP 16002778A JP 16002778 A JP16002778 A JP 16002778A JP S5588139 A JPS5588139 A JP S5588139A
Authority
JP
Japan
Prior art keywords
effective
written
instructions
judged
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16002778A
Other languages
Japanese (ja)
Other versions
JPS6053330B2 (en
Inventor
Hiroshi Matsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP53160027A priority Critical patent/JPS6053330B2/en
Publication of JPS5588139A publication Critical patent/JPS5588139A/en
Publication of JPS6053330B2 publication Critical patent/JPS6053330B2/en
Expired legal-status Critical Current

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Abstract

PURPOSE: To perform write operation with PROM connected to a unit by writing effective instructions in case that when a ROM unit is selected and its program is judged to be effective, any other instruction is not written at an assigned address.
CONSTITUTION: On the basis of a decision signal, program loader 15 discriminates whether a memory selected from memory 14 is RAM or PROM, and when the ROM unit is selected, its program is judged to be effective or not. When it is judged to be effective instructions, a previously-fixed logic state, e.g. "0" is written at an assigned address and write operation of following effective instructions is inhibited; and when effective insturction, it is judged whether any other instruction is written at the assigned address and if not, effective instructions are written. Consequently, instructions can be written by RAM program loader 15 with PROM connected to a processor.
COPYRIGHT: (C)1980,JPO&Japio
JP53160027A 1978-12-27 1978-12-27 Program writing method Expired JPS6053330B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53160027A JPS6053330B2 (en) 1978-12-27 1978-12-27 Program writing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53160027A JPS6053330B2 (en) 1978-12-27 1978-12-27 Program writing method

Publications (2)

Publication Number Publication Date
JPS5588139A true JPS5588139A (en) 1980-07-03
JPS6053330B2 JPS6053330B2 (en) 1985-11-25

Family

ID=15706369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53160027A Expired JPS6053330B2 (en) 1978-12-27 1978-12-27 Program writing method

Country Status (1)

Country Link
JP (1) JPS6053330B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59189445A (en) * 1983-04-12 1984-10-27 Mitsubishi Electric Corp Numerical controller
JPS60149244A (en) * 1984-01-13 1985-08-06 Matsushita Electric Works Ltd Program setting system for multiplex transmission system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59189445A (en) * 1983-04-12 1984-10-27 Mitsubishi Electric Corp Numerical controller
JPS60149244A (en) * 1984-01-13 1985-08-06 Matsushita Electric Works Ltd Program setting system for multiplex transmission system
JPH0544859B2 (en) * 1984-01-13 1993-07-07 Matsushita Electric Works Ltd

Also Published As

Publication number Publication date
JPS6053330B2 (en) 1985-11-25

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