JPS57198648A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57198648A
JPS57198648A JP56084025A JP8402581A JPS57198648A JP S57198648 A JPS57198648 A JP S57198648A JP 56084025 A JP56084025 A JP 56084025A JP 8402581 A JP8402581 A JP 8402581A JP S57198648 A JPS57198648 A JP S57198648A
Authority
JP
Japan
Prior art keywords
plating
resist
semiconductor device
wiring
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56084025A
Other languages
Japanese (ja)
Other versions
JPS6248899B2 (en
Inventor
Hiromichi Kono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56084025A priority Critical patent/JPS57198648A/en
Publication of JPS57198648A publication Critical patent/JPS57198648A/en
Publication of JPS6248899B2 publication Critical patent/JPS6248899B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Abstract

PURPOSE:To contrive the fineness of wiring and the improvement of yield by a method wherein the first resist mask is applied and a wiring layer is made by plating with the same thickness as that of the mask or thinner and the second resist mask is applied to provide a projected electrode by plating. CONSTITUTION:Pt wirings 2 exist on an Si substrate 1 formed elements. A photo resist pattern 3 with thicker than planned Au plating thickness or the same thickness is provided by selecting forming condition. After applying Au plating with predetermined thickness, the resist 3 is removed, and the second photo resist pattern 5 is made. At that time, no cracked sections exist at the Au cross section. Therefore, a thin film is acceptable and no pin holes are generated. Next, a projected electrode 6 is provided by Au plating to remove the resist and a semiconductor device is completed. In this composition, a semiconductor device having plating wiring can be made with good yield and high productivity.
JP56084025A 1981-06-01 1981-06-01 Manufacture of semiconductor device Granted JPS57198648A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56084025A JPS57198648A (en) 1981-06-01 1981-06-01 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56084025A JPS57198648A (en) 1981-06-01 1981-06-01 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57198648A true JPS57198648A (en) 1982-12-06
JPS6248899B2 JPS6248899B2 (en) 1987-10-16

Family

ID=13819011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56084025A Granted JPS57198648A (en) 1981-06-01 1981-06-01 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57198648A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120683A (en) * 1976-03-31 1977-10-11 Licentia Gmbh Method of making multiilayered metalic electrodes for semiconductor elements
JPS52128059A (en) * 1976-04-20 1977-10-27 Nec Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120683A (en) * 1976-03-31 1977-10-11 Licentia Gmbh Method of making multiilayered metalic electrodes for semiconductor elements
JPS52128059A (en) * 1976-04-20 1977-10-27 Nec Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS6248899B2 (en) 1987-10-16

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