JPS57170554A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57170554A
JPS57170554A JP56055550A JP5555081A JPS57170554A JP S57170554 A JPS57170554 A JP S57170554A JP 56055550 A JP56055550 A JP 56055550A JP 5555081 A JP5555081 A JP 5555081A JP S57170554 A JPS57170554 A JP S57170554A
Authority
JP
Japan
Prior art keywords
film
wire
plasma cvd
hole
si3n4
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56055550A
Other languages
Japanese (ja)
Inventor
Shigeru Takahashi
Kiichiro Mukai
Shinichi Muramatsu
Yuzuru Oji
Atsushi Hiraiwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56055550A priority Critical patent/JPS57170554A/en
Publication of JPS57170554A publication Critical patent/JPS57170554A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To optimize the stress distribution of a semiconductor device by opening a hole at a plasma CVD Si3N4 film on an Si substrate, forming a multilayer film wire conductor, forming a solder projection electrode through a metallic film on the prescribed position of the wire, and extending the wire conductor by at least 10mum from the metallic film. CONSTITUTION:A multilayer wire 3 made of Al, Ti, Cr or the like is formed through a plasma CVD Si3N4 film 2 on an Si substrate 1. Then, a plasma CVD Si3N4 4 having excellent mechanical strength is formed as a protective film on the overall surface, a connecting hole 5 is opened thereat, and a Ti 6 and a Cu 7 are sequentially covered in the prescribed thickness. The Ti 6 prevent the mutual diffusion between the wire 3 and the Cu 7. Then, a plasms CVD Si3N4 8 is superimposed, a resist mask 10 is covered, and a hole 9 is opened. Subsequently, plating films are laminated in the sequence of an Ni 11, an Sn 12 and a Pb 13, the resist 10 is removed, the Cu 7 and the Ti 6 are etched with the mask 8, a wire pattern is completed, and a solder projection electrode 14 is formed. In this case, particularly when a Cu-Ti film extends in the length longer than 20mum from the peripheral edge of the Ni film 11, it is extremely effective for the improvement of the stress distribution of the protective film under the solder electrode and for the prevention of the damage of the film.
JP56055550A 1981-04-15 1981-04-15 Semiconductor device Pending JPS57170554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56055550A JPS57170554A (en) 1981-04-15 1981-04-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56055550A JPS57170554A (en) 1981-04-15 1981-04-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57170554A true JPS57170554A (en) 1982-10-20

Family

ID=13001806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56055550A Pending JPS57170554A (en) 1981-04-15 1981-04-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57170554A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5124269A (en) * 1988-03-05 1992-06-23 Kanegafuchi Kagaku Kogyo Kabushiki Method of producing a semiconductor device using a wire mask having a specified diameter
US6410981B2 (en) 1997-10-24 2002-06-25 Nec Corporation Vented semiconductor device package having separate substrate, strengthening ring and cap structures
US7202421B2 (en) 2003-01-30 2007-04-10 Seiko Epson Corporation Electronic elements, method for manufacturing electronic elements, circuit substrates, method for manufacturing circuit substrates, electronic devices and method for manufacturing electronic devices

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5459080A (en) * 1977-10-19 1979-05-12 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5459080A (en) * 1977-10-19 1979-05-12 Nec Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5124269A (en) * 1988-03-05 1992-06-23 Kanegafuchi Kagaku Kogyo Kabushiki Method of producing a semiconductor device using a wire mask having a specified diameter
US6410981B2 (en) 1997-10-24 2002-06-25 Nec Corporation Vented semiconductor device package having separate substrate, strengthening ring and cap structures
US7202421B2 (en) 2003-01-30 2007-04-10 Seiko Epson Corporation Electronic elements, method for manufacturing electronic elements, circuit substrates, method for manufacturing circuit substrates, electronic devices and method for manufacturing electronic devices

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