JPS55111127A - Method for forming solder bump - Google Patents

Method for forming solder bump

Info

Publication number
JPS55111127A
JPS55111127A JP1820979A JP1820979A JPS55111127A JP S55111127 A JPS55111127 A JP S55111127A JP 1820979 A JP1820979 A JP 1820979A JP 1820979 A JP1820979 A JP 1820979A JP S55111127 A JPS55111127 A JP S55111127A
Authority
JP
Japan
Prior art keywords
temperature
layer
solder
photoresist
damages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1820979A
Other languages
Japanese (ja)
Inventor
Misao Saga
Akira Amano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP1820979A priority Critical patent/JPS55111127A/en
Publication of JPS55111127A publication Critical patent/JPS55111127A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To form a solder bump which is characterized by the features that a photoresist is readily removed and damages are not remained in characteristic checking, by melting a solder-plated layer at a specified temperature and curing it, thereafter melting the solder layer at a higher temperature and curing it again.
CONSTITUTION: A surface-protecting film 4 is further deposited on an Al wiring 3 which contacts with Si and the window portion of a surface-protecting film 2 on a Si substrate 1, and an underlying metal layer 5 is formed at said window portion. Thereafter, a Pb layer 6 and an Sn layer 7 are stacked by electric plating with a photoresist being a mask. Then, the plated layers 6 and 7 are melted at a temperature less than 320°C, and the photoresist is removed after said layers have been cooled and cured. At this stage, the characteristic check of the element is performed. Thereafter, the temperature is increased again, and the soldering layers are melted again at a temperature higher than the previous melting temperature (e.g., 330W 350°C for the solder comprising 90% of Pb and 10% of Sn), thereby a semi-circular solder bump 8 is obtained. In this constitution, even though damages are given in the characteristic check, the remnants of the damages are not remained.
COPYRIGHT: (C)1980,JPO&Japio
JP1820979A 1979-02-19 1979-02-19 Method for forming solder bump Pending JPS55111127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1820979A JPS55111127A (en) 1979-02-19 1979-02-19 Method for forming solder bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1820979A JPS55111127A (en) 1979-02-19 1979-02-19 Method for forming solder bump

Publications (1)

Publication Number Publication Date
JPS55111127A true JPS55111127A (en) 1980-08-27

Family

ID=11965253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1820979A Pending JPS55111127A (en) 1979-02-19 1979-02-19 Method for forming solder bump

Country Status (1)

Country Link
JP (1) JPS55111127A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps
US5071787A (en) * 1989-03-14 1991-12-10 Kabushiki Kaisha Toshiba Semiconductor device utilizing a face-down bonding and a method for manufacturing the same
US5289631A (en) * 1992-03-04 1994-03-01 Mcnc Method for testing, burn-in, and/or programming of integrated circuit chips
US5447264A (en) * 1994-07-01 1995-09-05 Mcnc Recessed via apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon
US5767010A (en) * 1995-03-20 1998-06-16 Mcnc Solder bump fabrication methods and structure including a titanium barrier layer
US5793116A (en) * 1996-05-29 1998-08-11 Mcnc Microelectronic packaging using arched solder columns
US5892179A (en) * 1995-04-05 1999-04-06 Mcnc Solder bumps and structures for integrated redistribution routing conductors
US5990472A (en) * 1997-09-29 1999-11-23 Mcnc Microelectronic radiation detectors for detecting and emitting radiation signals
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
US6429030B1 (en) 1999-02-08 2002-08-06 Motorola, Inc. Method for testing a semiconductor die using wells
US7495326B2 (en) 2002-10-22 2009-02-24 Unitive International Limited Stacked electronic structures including offset substrates
US8674494B2 (en) 2011-08-31 2014-03-18 Samsung Electronics Co., Ltd. Semiconductor package having supporting plate and method of forming the same

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps
US5071787A (en) * 1989-03-14 1991-12-10 Kabushiki Kaisha Toshiba Semiconductor device utilizing a face-down bonding and a method for manufacturing the same
US5289631A (en) * 1992-03-04 1994-03-01 Mcnc Method for testing, burn-in, and/or programming of integrated circuit chips
US5374893A (en) * 1992-03-04 1994-12-20 Mcnc Apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon
US5381946A (en) * 1992-03-04 1995-01-17 Mcnc Method of forming differing volume solder bumps
US5447264A (en) * 1994-07-01 1995-09-05 Mcnc Recessed via apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon
US6222279B1 (en) 1995-03-20 2001-04-24 Mcnc Solder bump fabrication methods and structures including a titanium barrier layer
US5767010A (en) * 1995-03-20 1998-06-16 Mcnc Solder bump fabrication methods and structure including a titanium barrier layer
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
US6392163B1 (en) 1995-04-04 2002-05-21 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps
US5892179A (en) * 1995-04-05 1999-04-06 Mcnc Solder bumps and structures for integrated redistribution routing conductors
US6329608B1 (en) 1995-04-05 2001-12-11 Unitive International Limited Key-shaped solder bumps and under bump metallurgy
US6389691B1 (en) 1995-04-05 2002-05-21 Unitive International Limited Methods for forming integrated redistribution routing conductors and solder bumps
US5793116A (en) * 1996-05-29 1998-08-11 Mcnc Microelectronic packaging using arched solder columns
US5990472A (en) * 1997-09-29 1999-11-23 Mcnc Microelectronic radiation detectors for detecting and emitting radiation signals
US6429030B1 (en) 1999-02-08 2002-08-06 Motorola, Inc. Method for testing a semiconductor die using wells
US7495326B2 (en) 2002-10-22 2009-02-24 Unitive International Limited Stacked electronic structures including offset substrates
US8674494B2 (en) 2011-08-31 2014-03-18 Samsung Electronics Co., Ltd. Semiconductor package having supporting plate and method of forming the same
US9412720B2 (en) 2011-08-31 2016-08-09 Samsung Electronics Co., Ltd. Semiconductor package having supporting plate and method of forming the same

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