JPS5674945A - Electrode forming method of semiconductor element - Google Patents
Electrode forming method of semiconductor elementInfo
- Publication number
- JPS5674945A JPS5674945A JP15161079A JP15161079A JPS5674945A JP S5674945 A JPS5674945 A JP S5674945A JP 15161079 A JP15161079 A JP 15161079A JP 15161079 A JP15161079 A JP 15161079A JP S5674945 A JPS5674945 A JP S5674945A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- layer
- electrode
- corrosion
- lateral side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To install a main electrode having a strong adhesion and an effective junction performance and to prevent an internal wiring from corrosion by a method wherein a lateral side of a barrier layer (chemically a base metal) at the underneath of a main electrode is prevented from an excessive corrosion. CONSTITUTION:An SiO2 film 2, an Al wiring 3, and an opened PSG 4 are laid upon an Si substrate 1 and further, a Cr 6 and Cu 7 are laminated as a barrier layer. Following this, an insulating mask 10 having a concentrical annular hole 9 is installed and plated with Au. At this time, Au is precipitated on the Cu layer 7 of an opening 8 of the mask 10 and in the annular hole 9 and Au is precipitated in lateral directions to be formed into one body, thus, a part 10a of the mask being embedded to form a main electrode 11. Next thereto, the mask 10 is removed and then, Cu and Cr are sequentially, selectively etched. At this tmie, a lateral side of the Cu 7 is etched by means of a local battery, however, it is stopped before the mask 10a. The mask 10a is removed, thus, completing an electrode 13 composed of a barrier layer 12 and the Au 11. The electrode has no sharply etched lateral side and the area of the layer 12 is wide, as a result adhesion is strong, thus, producing no corrosion in the Al wiring 3 under the layer 12.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15161079A JPS5674945A (en) | 1979-11-22 | 1979-11-22 | Electrode forming method of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15161079A JPS5674945A (en) | 1979-11-22 | 1979-11-22 | Electrode forming method of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5674945A true JPS5674945A (en) | 1981-06-20 |
Family
ID=15522289
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15161079A Pending JPS5674945A (en) | 1979-11-22 | 1979-11-22 | Electrode forming method of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5674945A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6356941A (en) * | 1986-08-28 | 1988-03-11 | Fujitsu Ltd | Manufacture of semiconductor device |
US5316974A (en) * | 1988-12-19 | 1994-05-31 | Texas Instruments Incorporated | Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer |
-
1979
- 1979-11-22 JP JP15161079A patent/JPS5674945A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6356941A (en) * | 1986-08-28 | 1988-03-11 | Fujitsu Ltd | Manufacture of semiconductor device |
US5316974A (en) * | 1988-12-19 | 1994-05-31 | Texas Instruments Incorporated | Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer |
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