JPS57157556A - Amplifying circuit - Google Patents

Amplifying circuit

Info

Publication number
JPS57157556A
JPS57157556A JP56042175A JP4217581A JPS57157556A JP S57157556 A JPS57157556 A JP S57157556A JP 56042175 A JP56042175 A JP 56042175A JP 4217581 A JP4217581 A JP 4217581A JP S57157556 A JPS57157556 A JP S57157556A
Authority
JP
Japan
Prior art keywords
terminals
gate
grounded
series
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56042175A
Other languages
Japanese (ja)
Inventor
Shunichi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56042175A priority Critical patent/JPS57157556A/en
Publication of JPS57157556A publication Critical patent/JPS57157556A/en
Pending legal-status Critical Current

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Landscapes

  • Amplifiers (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To obtain a voltage amplifying circuit having high sensitivity, less necessary power and high performance by forming the circuit of three FETs connected in series with each other, applying the prescribed voltage to one terminals, ground the other terminals, and connecting capacitors ground at one respective teriminals to the two connecting points of the FETs connected in series.
CONSTITUTION: The first, second and third FET elements Q1, Q2, Q3 are connected in series with each other, a power source is connected to the other terminal of the element Q1, and the other terminal of the element Q3 is grounded. Grounded capacitors C1, C2 in which the ground capacitances are set at C2> C1 are connected to the connecting points of the elements Q1 and Q2, Q2 and Q3, and the other terminals are grounded. Subsequently, a clock signals ϕ1 is inputted to the gate of the element Q1, an input signal Vin is applied to the gate of the element Q2, and a clock signal ϕ2 not superposed with the signal ϕ1 is inputted to the gate of the element Q3. Thus, an output signal V0 amplified at a rate of C2>C1 with respect to the varied amount of the input signal Vin can be obtained from the connecting point of the elements Q1 and Q2.
COPYRIGHT: (C)1982,JPO&Japio
JP56042175A 1981-03-23 1981-03-23 Amplifying circuit Pending JPS57157556A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56042175A JPS57157556A (en) 1981-03-23 1981-03-23 Amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56042175A JPS57157556A (en) 1981-03-23 1981-03-23 Amplifying circuit

Publications (1)

Publication Number Publication Date
JPS57157556A true JPS57157556A (en) 1982-09-29

Family

ID=12628637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56042175A Pending JPS57157556A (en) 1981-03-23 1981-03-23 Amplifying circuit

Country Status (1)

Country Link
JP (1) JPS57157556A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4911472A (en) * 1987-11-25 1990-03-27 Nippon Seiko Kabushiki Kaisha Slider for passive seat belt system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4911472A (en) * 1987-11-25 1990-03-27 Nippon Seiko Kabushiki Kaisha Slider for passive seat belt system

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