JPS57151874A - Testing device for logic circuit - Google Patents

Abstract

PURPOSE:To perform the simultaneous test, by controlling the inhibition, release, and the like of a timing signal by a coincident signal based on the timing signal and a test result signal of a testing pattern, and synchronizing a plurality of units under test. CONSTITUTION:The test pattern is read out of a test pattern memory part 4 through a control part 5 in a test pattern generating part 1, in response to a timing pulse from a timing pulse generator 2. The test pattern is supplied to pin electronics 3 and 3'. The logic circuits of the units under test 7 and 7' are tested based on the timing signals from timing signal inhibiting circuits 8 and 8'. Good signals or poor signals are monitored by coincidence detecting circuits 6 and 6', and the coincident signals are outputted. The circuit 8 or 8' which corresponds to said coincident signals is inhibited. Said inhibition is released by both coincident signals through an AND gate 9. The test of the next step is performed by the memory part 4 and the control part 5 under the state the units under test 7 and 7' are synchronized. Thus, a plurality of the units under test can be positively tested under the synchronized state.