JPS5794997A - Memory test system - Google Patents

Memory test system

Info

Publication number
JPS5794997A
JPS5794997A JP55170376A JP17037680A JPS5794997A JP S5794997 A JPS5794997 A JP S5794997A JP 55170376 A JP55170376 A JP 55170376A JP 17037680 A JP17037680 A JP 17037680A JP S5794997 A JPS5794997 A JP S5794997A
Authority
JP
Japan
Prior art keywords
clock
latch circuits
normal
latch
closest
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55170376A
Other languages
Japanese (ja)
Other versions
JPS6132759B2 (en
Inventor
Takashi Ibi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55170376A priority Critical patent/JPS5794997A/en
Publication of JPS5794997A publication Critical patent/JPS5794997A/en
Publication of JPS6132759B2 publication Critical patent/JPS6132759B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To achieve a flexible high-level test with simple constitution by supplying a normal testing clock to the closest latch circuit to a memory to be tested among latch circuits and a pseudo clock to other latch circuits. CONSTITUTION:The closest latch circuit to an RAM is supplied with a normal testing clock, and leading latch circuits L0 and L1 are supplied with a pseudo clock having different timing from the normal clock. Consequently, all stages of the latch circuits are tested to obtain a high-level test result, and a selector, etc., is inserted at an optional place to improve versatility when a testing circuit is incorporated.
JP55170376A 1980-12-03 1980-12-03 Memory test system Granted JPS5794997A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55170376A JPS5794997A (en) 1980-12-03 1980-12-03 Memory test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55170376A JPS5794997A (en) 1980-12-03 1980-12-03 Memory test system

Publications (2)

Publication Number Publication Date
JPS5794997A true JPS5794997A (en) 1982-06-12
JPS6132759B2 JPS6132759B2 (en) 1986-07-29

Family

ID=15903785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55170376A Granted JPS5794997A (en) 1980-12-03 1980-12-03 Memory test system

Country Status (1)

Country Link
JP (1) JPS5794997A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03203548A (en) * 1989-12-27 1991-09-05 Mitsubishi Electric Corp Motor

Also Published As

Publication number Publication date
JPS6132759B2 (en) 1986-07-29

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