JPS57145327A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57145327A
JPS57145327A JP2991681A JP2991681A JPS57145327A JP S57145327 A JPS57145327 A JP S57145327A JP 2991681 A JP2991681 A JP 2991681A JP 2991681 A JP2991681 A JP 2991681A JP S57145327 A JPS57145327 A JP S57145327A
Authority
JP
Japan
Prior art keywords
layer
resist
flat
insulative
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2991681A
Other languages
Japanese (ja)
Inventor
Tadashi Serikawa
Toshiaki Taniuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP2991681A priority Critical patent/JPS57145327A/en
Publication of JPS57145327A publication Critical patent/JPS57145327A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To allow the high yield manufacture of high reliability semiconductor device with high withstand voltage, by flattening the surface of semiconductor element. CONSTITUTION:A conductive layer 12 is formed on a semiconductor substrate 11. Next a resist 13 treated with patterning is formed on this layer 12, and then etching is done with the resist 13 as a mask to form a conductive layer 12a with bevel trail. Subsequently an insulative layer 14 is formed on the whole sunface by sputtering. In this case, the insulative layer 14a formed at the bevel trail has minute density by the same degree as the insulative layer 14b and 14c formed on a flat surface. On the contrary, the insulative layer 14d formed on the side of the resist 13 has less density. Consequently, when the substrate 11 is etched, only the layer 14d is selectively removed. Next the layer 14c on the upper surface is lifted off with the resist 13. As the result, the structure having a flat element surface is obtained. Thus, a flat conductive layer 16 is formed on the substrate via the insulating layer 15.
JP2991681A 1981-03-04 1981-03-04 Manufacture of semiconductor device Pending JPS57145327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2991681A JPS57145327A (en) 1981-03-04 1981-03-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2991681A JPS57145327A (en) 1981-03-04 1981-03-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57145327A true JPS57145327A (en) 1982-09-08

Family

ID=12289311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2991681A Pending JPS57145327A (en) 1981-03-04 1981-03-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57145327A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60261156A (en) * 1984-06-08 1985-12-24 Nippon Telegr & Teleph Corp <Ntt> Method for forming multiple-layer wiring
JPS6189634A (en) * 1984-10-08 1986-05-07 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS6324625A (en) * 1986-07-16 1988-02-02 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH02224357A (en) * 1989-02-27 1990-09-06 Mitsubishi Electric Corp Manufacture of semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5333581A (en) * 1976-09-10 1978-03-29 Hitachi Ltd Production of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5333581A (en) * 1976-09-10 1978-03-29 Hitachi Ltd Production of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60261156A (en) * 1984-06-08 1985-12-24 Nippon Telegr & Teleph Corp <Ntt> Method for forming multiple-layer wiring
JPS6189634A (en) * 1984-10-08 1986-05-07 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS6324625A (en) * 1986-07-16 1988-02-02 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH02224357A (en) * 1989-02-27 1990-09-06 Mitsubishi Electric Corp Manufacture of semiconductor device

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