JPS57176745A - Manufacture of multilayer wiring - Google Patents

Manufacture of multilayer wiring

Info

Publication number
JPS57176745A
JPS57176745A JP6106781A JP6106781A JPS57176745A JP S57176745 A JPS57176745 A JP S57176745A JP 6106781 A JP6106781 A JP 6106781A JP 6106781 A JP6106781 A JP 6106781A JP S57176745 A JPS57176745 A JP S57176745A
Authority
JP
Japan
Prior art keywords
layer
wiring
lift
multilayer wiring
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6106781A
Other languages
Japanese (ja)
Other versions
JPS639660B2 (en
Inventor
Kohei Ebara
Manabu Henmi
Susumu Muramoto
Seitaro Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP6106781A priority Critical patent/JPS57176745A/en
Priority to US06/369,235 priority patent/US4564997A/en
Priority to CA000401294A priority patent/CA1204883A/en
Priority to EP82302044A priority patent/EP0063917B1/en
Priority to DE8282302044T priority patent/DE3271995D1/en
Publication of JPS57176745A publication Critical patent/JPS57176745A/en
Publication of JPS639660B2 publication Critical patent/JPS639660B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To enable to form a wiring of multilayers in a multilayer wiring of a semiconductor integrated circuit device by reducing the width of the wire by a lift-off method, increasing the thickness of the wiring and flattening the upper surface of the wiring layer. CONSTITUTION:A conductor layer 3a and a resist layer 7a are laminated on an insulating of layer 2 on a semiconductor substrate 1, the layer 3a is patterned by a resist 7a, an insulating layer 4a is formed by low temperature chemical reaction such as an ERC type plasma accumulation method, is then lifted off, and a flat wiring surface is formed. After the layer 3a is etched, the resist mask 7a is used as a lift-off material to bury the insulating layer in the conductor layer, and the accumulation method having good directivity due to low temperature chemical reaction such as ERC type plasma accumulation method is used. Accordingly, the flatnes after the lift-off is improved, and the multilayer wiring can be formed by repeating the lamination of the insulating layer and the conductor layer similarly and the patterning of the layers.
JP6106781A 1981-04-21 1981-04-21 Manufacture of multilayer wiring Granted JPS57176745A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP6106781A JPS57176745A (en) 1981-04-21 1981-04-21 Manufacture of multilayer wiring
US06/369,235 US4564997A (en) 1981-04-21 1982-04-16 Semiconductor device and manufacturing process thereof
CA000401294A CA1204883A (en) 1981-04-21 1982-04-20 Semiconductor device and manufacturing process thereof
EP82302044A EP0063917B1 (en) 1981-04-21 1982-04-21 Method of manufacturing a semiconductor device
DE8282302044T DE3271995D1 (en) 1981-04-21 1982-04-21 Method of manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6106781A JPS57176745A (en) 1981-04-21 1981-04-21 Manufacture of multilayer wiring

Publications (2)

Publication Number Publication Date
JPS57176745A true JPS57176745A (en) 1982-10-30
JPS639660B2 JPS639660B2 (en) 1988-03-01

Family

ID=13160429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6106781A Granted JPS57176745A (en) 1981-04-21 1981-04-21 Manufacture of multilayer wiring

Country Status (1)

Country Link
JP (1) JPS57176745A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63219140A (en) * 1987-03-06 1988-09-12 Matsushita Electronics Corp Formation of multilayer interconnection of semiconductor element
JPH04229625A (en) * 1990-04-30 1992-08-19 American Teleph & Telegr Co <Att> Manufacture of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5495185A (en) * 1978-01-13 1979-07-27 Hitachi Ltd Production of semiconductor device
JPS5568655A (en) * 1978-11-20 1980-05-23 Fujitsu Ltd Manufacturing method of wiring

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5495185A (en) * 1978-01-13 1979-07-27 Hitachi Ltd Production of semiconductor device
JPS5568655A (en) * 1978-11-20 1980-05-23 Fujitsu Ltd Manufacturing method of wiring

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63219140A (en) * 1987-03-06 1988-09-12 Matsushita Electronics Corp Formation of multilayer interconnection of semiconductor element
JPH04229625A (en) * 1990-04-30 1992-08-19 American Teleph & Telegr Co <Att> Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS639660B2 (en) 1988-03-01

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