JPS57133656A - Semiconductor integrated circuit incorporated with test circuit - Google Patents
Semiconductor integrated circuit incorporated with test circuitInfo
- Publication number
- JPS57133656A JPS57133656A JP56019219A JP1921981A JPS57133656A JP S57133656 A JPS57133656 A JP S57133656A JP 56019219 A JP56019219 A JP 56019219A JP 1921981 A JP1921981 A JP 1921981A JP S57133656 A JPS57133656 A JP S57133656A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- input
- output
- latch circuit
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To reduce the number of pins while increasing circuits which can be mounted to the inside by mounting a circuit latching the output of an input level detecting circuit to a multifunctional input terminal and using the output of the latch circuit as signals for testing the inside. CONSTITUTION:The multifunctional input terminal IN2 is connected to the input level detecting circuit consisting of E/DMOS elements N21, N22 and a circuit G21 for a function. The output of the level detecting circuit is connected to the set input of the flip-flop type latch circuit formed by NAND gates G22, G23, and signals activating a test circuit are outputted to a terminal OUT22 from the latch circuit. When voltage exceeding VCC is applied to the IN2, the latch circuit is set, and the OUT22 is at a low level, and thereafter continues a test mode condition until reset signals R are inputted. On the other hand, output signals corresponding to input are outputted to the OUT21 even at the time of a test mode. Accordingly, the number of the pins can be reduced and the mounting density of the internal circuits can be increased because a fixed level need not be inputted to the input terminal at all times when the test mode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56019219A JPS57133656A (en) | 1981-02-12 | 1981-02-12 | Semiconductor integrated circuit incorporated with test circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56019219A JPS57133656A (en) | 1981-02-12 | 1981-02-12 | Semiconductor integrated circuit incorporated with test circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57133656A true JPS57133656A (en) | 1982-08-18 |
Family
ID=11993248
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56019219A Pending JPS57133656A (en) | 1981-02-12 | 1981-02-12 | Semiconductor integrated circuit incorporated with test circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57133656A (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0141681A2 (en) * | 1983-11-07 | 1985-05-15 | Texas Instruments Incorporated | Test input multiplexing circuit |
JPS6154468A (en) * | 1984-08-25 | 1986-03-18 | Fujitsu Ltd | Semiconductor device |
JPS61161470A (en) * | 1985-01-10 | 1986-07-22 | Nippon Denso Co Ltd | Semiconductor integrated circuit device |
JPS61264270A (en) * | 1985-05-17 | 1986-11-22 | Matsushita Electronics Corp | Testing method for semiconductor integrated circuit |
EP0212997A2 (en) * | 1985-06-20 | 1987-03-04 | Fujitsu Limited | Semiconductor integrated circuit adapted to carry out a test operation |
JPS6438674A (en) * | 1987-08-04 | 1989-02-08 | Nippon Electric Ic Microcomput | Semiconductor integrated circuit |
JPS6466579A (en) * | 1987-09-07 | 1989-03-13 | Nippon Electric Ic Microcomput | Test circuit |
JPH02162273A (en) * | 1988-08-30 | 1990-06-21 | Goldstar Electron Co Ltd | Test mode function execution input circuit |
JPH02190783A (en) * | 1988-12-14 | 1990-07-26 | Samsung Electron Co Ltd | Multiple test mode selection circuit |
JPH04128670A (en) * | 1990-09-20 | 1992-04-30 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit |
JPH05343622A (en) * | 1992-06-10 | 1993-12-24 | Nec Corp | Semiconductor integrated circuit having self-diagnostic circuit |
WO2004001568A3 (en) * | 2002-06-21 | 2004-03-18 | Melexis Nv | Single pin multilevel integrated circuit test interface |
JP2008266991A (en) * | 2007-04-20 | 2008-11-06 | Maeda Road Constr Co Ltd | Device for adjusting mold form member height |
-
1981
- 1981-02-12 JP JP56019219A patent/JPS57133656A/en active Pending
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4612499A (en) * | 1983-11-07 | 1986-09-16 | Texas Instruments Incorporated | Test input demultiplexing circuit |
EP0141681A2 (en) * | 1983-11-07 | 1985-05-15 | Texas Instruments Incorporated | Test input multiplexing circuit |
JPH0349393B2 (en) * | 1984-08-25 | 1991-07-29 | Fujitsu Ltd | |
JPS6154468A (en) * | 1984-08-25 | 1986-03-18 | Fujitsu Ltd | Semiconductor device |
JPS61161470A (en) * | 1985-01-10 | 1986-07-22 | Nippon Denso Co Ltd | Semiconductor integrated circuit device |
JPS61264270A (en) * | 1985-05-17 | 1986-11-22 | Matsushita Electronics Corp | Testing method for semiconductor integrated circuit |
EP0212997A2 (en) * | 1985-06-20 | 1987-03-04 | Fujitsu Limited | Semiconductor integrated circuit adapted to carry out a test operation |
JPS6438674A (en) * | 1987-08-04 | 1989-02-08 | Nippon Electric Ic Microcomput | Semiconductor integrated circuit |
JPS6466579A (en) * | 1987-09-07 | 1989-03-13 | Nippon Electric Ic Microcomput | Test circuit |
JPH02162273A (en) * | 1988-08-30 | 1990-06-21 | Goldstar Electron Co Ltd | Test mode function execution input circuit |
JPH02190783A (en) * | 1988-12-14 | 1990-07-26 | Samsung Electron Co Ltd | Multiple test mode selection circuit |
JPH04128670A (en) * | 1990-09-20 | 1992-04-30 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit |
JPH05343622A (en) * | 1992-06-10 | 1993-12-24 | Nec Corp | Semiconductor integrated circuit having self-diagnostic circuit |
WO2004001568A3 (en) * | 2002-06-21 | 2004-03-18 | Melexis Nv | Single pin multilevel integrated circuit test interface |
JP2008266991A (en) * | 2007-04-20 | 2008-11-06 | Maeda Road Constr Co Ltd | Device for adjusting mold form member height |
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